ssc_step_size 206 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c u64 ssc_step_size; ssc_step_size 221 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c ssc_step_size = regs->decimal_div_start; ssc_step_size 222 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c ssc_step_size *= (1 << config->frac_bits); ssc_step_size 223 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c ssc_step_size += frac; ssc_step_size 224 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c ssc_step_size *= config->ssc_offset; ssc_step_size 225 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c ssc_step_size *= (config->ssc_adj_per + 1); ssc_step_size 226 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1)); ssc_step_size 227 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000); ssc_step_size 231 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF); ssc_step_size 232 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8); ssc_step_size 241 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c ssc_per, (u32)ssc_step_size, config->ssc_adj_per); ssc_step_size 90 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u32 ssc_step_size; ssc_step_size 296 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->out.ssc_step_size = step_size; ssc_step_size 412 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c data = pout->ssc_step_size; ssc_step_size 415 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c data = (pout->ssc_step_size >> 8);