srxx_com_ctl      317 arch/mips/cavium-octeon/executive/cvmx-spi.c 		union cvmx_srxx_com_ctl srxx_com_ctl;
srxx_com_ctl      321 arch/mips/cavium-octeon/executive/cvmx-spi.c 		srxx_com_ctl.u64 = 0;
srxx_com_ctl      322 arch/mips/cavium-octeon/executive/cvmx-spi.c 		srxx_com_ctl.s.prts = num_ports - 1;
srxx_com_ctl      323 arch/mips/cavium-octeon/executive/cvmx-spi.c 		srxx_com_ctl.s.st_en = 0;
srxx_com_ctl      324 arch/mips/cavium-octeon/executive/cvmx-spi.c 		srxx_com_ctl.s.inf_en = 0;
srxx_com_ctl      325 arch/mips/cavium-octeon/executive/cvmx-spi.c 		cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
srxx_com_ctl      582 arch/mips/cavium-octeon/executive/cvmx-spi.c 		union cvmx_srxx_com_ctl srxx_com_ctl;
srxx_com_ctl      586 arch/mips/cavium-octeon/executive/cvmx-spi.c 		srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
srxx_com_ctl      587 arch/mips/cavium-octeon/executive/cvmx-spi.c 		srxx_com_ctl.s.inf_en = 1;
srxx_com_ctl      588 arch/mips/cavium-octeon/executive/cvmx-spi.c 		srxx_com_ctl.s.st_en = 1;
srxx_com_ctl      589 arch/mips/cavium-octeon/executive/cvmx-spi.c 		cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
srxx_com_ctl      640 arch/mips/cavium-octeon/executive/cvmx-spi.c 		union cvmx_srxx_com_ctl srxx_com_ctl;
srxx_com_ctl      641 arch/mips/cavium-octeon/executive/cvmx-spi.c 		srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
srxx_com_ctl      642 arch/mips/cavium-octeon/executive/cvmx-spi.c 		srxx_com_ctl.s.inf_en = 1;
srxx_com_ctl      643 arch/mips/cavium-octeon/executive/cvmx-spi.c 		cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);