sregs_base         28 arch/arm/mach-highbank/highbank.c void __iomem *sregs_base;
sregs_base         99 arch/arm/mach-highbank/highbank.c 		val = readl(sregs_base + reg);
sregs_base        100 arch/arm/mach-highbank/highbank.c 		writel(val | 0xff01, sregs_base + reg);
sregs_base        143 arch/arm/mach-highbank/highbank.c 	sregs_base = of_iomap(np, 0);
sregs_base        144 arch/arm/mach-highbank/highbank.c 	WARN_ON(!sregs_base);
sregs_base         14 arch/arm/mach-highbank/sysregs.h extern void __iomem *sregs_base;
sregs_base         33 arch/arm/mach-highbank/sysregs.h 		writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
sregs_base         42 arch/arm/mach-highbank/sysregs.h 		writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu));
sregs_base         47 arch/arm/mach-highbank/sysregs.h 	writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
sregs_base         53 arch/arm/mach-highbank/sysregs.h 	writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
sregs_base         59 arch/arm/mach-highbank/sysregs.h 	writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
sregs_base         65 arch/arm/mach-highbank/sysregs.h 	writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
sregs_base         71 arch/arm/mach-highbank/sysregs.h 	writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ);