src_reloc 2800 drivers/gpu/drm/radeon/evergreen_cs.c struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc; src_reloc 2855 drivers/gpu/drm/radeon/evergreen_cs.c r = r600_dma_cs_next_reloc(p, &src_reloc); src_reloc 2873 drivers/gpu/drm/radeon/evergreen_cs.c if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { src_reloc 2875 drivers/gpu/drm/radeon/evergreen_cs.c src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); src_reloc 2884 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); src_reloc 2886 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; src_reloc 2896 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); src_reloc 2906 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); src_reloc 2907 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; src_reloc 2913 drivers/gpu/drm/radeon/evergreen_cs.c if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { src_reloc 2915 drivers/gpu/drm/radeon/evergreen_cs.c src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); src_reloc 2932 drivers/gpu/drm/radeon/evergreen_cs.c if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) { src_reloc 2934 drivers/gpu/drm/radeon/evergreen_cs.c src_offset + count, radeon_bo_size(src_reloc->robj)); src_reloc 2943 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); src_reloc 2945 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; src_reloc 2955 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); src_reloc 2956 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; src_reloc 2976 drivers/gpu/drm/radeon/evergreen_cs.c if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { src_reloc 2978 drivers/gpu/drm/radeon/evergreen_cs.c src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); src_reloc 2993 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); src_reloc 2996 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; src_reloc 3016 drivers/gpu/drm/radeon/evergreen_cs.c if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { src_reloc 3018 drivers/gpu/drm/radeon/evergreen_cs.c src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); src_reloc 3033 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); src_reloc 3034 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; src_reloc 3047 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); src_reloc 3053 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); src_reloc 3054 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; src_reloc 3078 drivers/gpu/drm/radeon/evergreen_cs.c if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { src_reloc 3080 drivers/gpu/drm/radeon/evergreen_cs.c src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); src_reloc 3095 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); src_reloc 3096 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; src_reloc 3107 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); src_reloc 3117 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); src_reloc 3118 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; src_reloc 3124 drivers/gpu/drm/radeon/evergreen_cs.c if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { src_reloc 3126 drivers/gpu/drm/radeon/evergreen_cs.c src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); src_reloc 3143 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); src_reloc 3165 drivers/gpu/drm/radeon/evergreen_cs.c if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { src_reloc 3167 drivers/gpu/drm/radeon/evergreen_cs.c src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); src_reloc 3182 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); src_reloc 3183 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; src_reloc 2381 drivers/gpu/drm/radeon/r600_cs.c struct radeon_bo_list *src_reloc, *dst_reloc; src_reloc 2428 drivers/gpu/drm/radeon/r600_cs.c r = r600_dma_cs_next_reloc(p, &src_reloc); src_reloc 2445 drivers/gpu/drm/radeon/r600_cs.c ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); src_reloc 2455 drivers/gpu/drm/radeon/r600_cs.c ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc); src_reloc 2456 drivers/gpu/drm/radeon/r600_cs.c ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; src_reloc 2471 drivers/gpu/drm/radeon/r600_cs.c ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); src_reloc 2473 drivers/gpu/drm/radeon/r600_cs.c ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; src_reloc 2482 drivers/gpu/drm/radeon/r600_cs.c ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); src_reloc 2483 drivers/gpu/drm/radeon/r600_cs.c ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff; src_reloc 2488 drivers/gpu/drm/radeon/r600_cs.c if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { src_reloc 2490 drivers/gpu/drm/radeon/r600_cs.c src_offset + (count * 4), radeon_bo_size(src_reloc->robj));