src_ref_clk       314 drivers/phy/mediatek/phy-mtk-tphy.c 	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
src_ref_clk       375 drivers/phy/mediatek/phy-mtk-tphy.c 		tmp = tphy->src_ref_clk * tphy->src_coef;
src_ref_clk       384 drivers/phy/mediatek/phy-mtk-tphy.c 		tphy->src_ref_clk, tphy->src_coef);
src_ref_clk      1110 drivers/phy/mediatek/phy-mtk-tphy.c 	tphy->src_ref_clk = U3P_REF_CLK;
src_ref_clk      1114 drivers/phy/mediatek/phy-mtk-tphy.c 		&tphy->src_ref_clk);
src_ref_clk       112 drivers/phy/mediatek/phy-mtk-xsphy.c 	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
src_ref_clk       168 drivers/phy/mediatek/phy-mtk-xsphy.c 		tmp = xsphy->src_ref_clk * xsphy->src_coef;
src_ref_clk       177 drivers/phy/mediatek/phy-mtk-xsphy.c 		xsphy->src_ref_clk, xsphy->src_coef);
src_ref_clk       526 drivers/phy/mediatek/phy-mtk-xsphy.c 	xsphy->src_ref_clk = XSP_REF_CLK;
src_ref_clk       530 drivers/phy/mediatek/phy-mtk-xsphy.c 				 &xsphy->src_ref_clk);