src_pll_id        211 drivers/gpu/drm/msm/dsi/dsi.h int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
src_pll_id        124 drivers/gpu/drm/msm/dsi/dsi_manager.c static int enable_phy(struct msm_dsi *msm_dsi, int src_pll_id,
src_pll_id        133 drivers/gpu/drm/msm/dsi/dsi_manager.c 	ret = msm_dsi_phy_enable(msm_dsi->phy, src_pll_id, &clk_req);
src_pll_id        146 drivers/gpu/drm/msm/dsi/dsi_manager.c 	int src_pll_id = IS_DUAL_DSI() ? DSI_CLOCK_MASTER : id;
src_pll_id        159 drivers/gpu/drm/msm/dsi/dsi_manager.c 			ret = enable_phy(mdsi, src_pll_id,
src_pll_id        163 drivers/gpu/drm/msm/dsi/dsi_manager.c 			ret = enable_phy(sdsi, src_pll_id,
src_pll_id        172 drivers/gpu/drm/msm/dsi/dsi_manager.c 		ret = enable_phy(msm_dsi, src_pll_id, &shared_timings[id]);
src_pll_id        665 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
src_pll_id        688 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 	ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req);
src_pll_id         21 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h 	int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
src_pll_id         87 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
src_pll_id         50 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
src_pll_id        106 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 	msm_dsi_phy_set_src_pll(phy, src_pll_id,
src_pll_id         66 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
src_pll_id         86 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c 	msm_dsi_phy_set_src_pll(phy, src_pll_id,
src_pll_id         61 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
src_pll_id        108 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c 	msm_dsi_phy_set_src_pll(phy, src_pll_id,
src_pll_id        120 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,