src_edc            31 drivers/dma/iop-adma.h #define AAU_SAR_EDCR(src_edc)	(chan->mmr_base + (0x02c + ((src_edc-4) << 2)))
src_edc           116 drivers/dma/iop-adma.h 	} src_edc[31];
src_edc           430 drivers/dma/iop-adma.h 		return hw_desc.aau->src_edc[__desc_idx(src_idx)].src_addr;
src_edc           439 drivers/dma/iop-adma.h 		hw_desc->src_edc[__desc_idx(src_idx)].src_addr = addr;
src_edc           497 drivers/dma/iop-adma.h 		hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr;
src_edc           502 drivers/dma/iop-adma.h 			hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
src_edc           511 drivers/dma/iop-adma.h 		hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr;
src_edc           523 drivers/dma/iop-adma.h 		hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr;
src_edc           604 drivers/dma/iop-adma.h 		hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
src_edc           608 drivers/dma/iop-adma.h 			hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
src_edc           611 drivers/dma/iop-adma.h 		hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0;
src_edc           616 drivers/dma/iop-adma.h 		hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0;