srbarea0           57 arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h 	u32	srbarea0;	/* 0x104 - SRAM base addr reg ext address 0 */
srbarea0          106 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c 	out_be32(&l2ctlr->srbarea0,