srbar0             56 arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h 	u32	srbar0;		/* 0x100 - SRAM base address 0 */
srbar0             99 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c 	out_be32(&l2ctlr->srbar0,