sram_sel           59 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h #define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) 				\
sram_sel           65 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 			(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); 		\
sram_sel           69 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h #define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) 			\
sram_sel           77 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 			(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); 		\
sram_sel          633 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
sram_sel          644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
sram_sel          646 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
sram_sel          675 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
sram_sel          678 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
sram_sel          681 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
sram_sel          684 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
sram_sel          612 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		uint8_t sram_sel, uint8_t indirect)
sram_sel          644 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
sram_sel          648 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
sram_sel          652 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
sram_sel          656 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);