sram_data_reg_offset 242 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c unsigned int *sram_data_reg_offset, sram_data_reg_offset 253 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = 0; sram_data_reg_offset 260 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); sram_data_reg_offset 266 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); sram_data_reg_offset 272 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); sram_data_reg_offset 278 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); sram_data_reg_offset 284 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); sram_data_reg_offset 290 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); sram_data_reg_offset 296 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); sram_data_reg_offset 566 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c unsigned int *sram_data_reg_offset, sram_data_reg_offset 577 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = 0; sram_data_reg_offset 584 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); sram_data_reg_offset 590 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); sram_data_reg_offset 596 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); sram_data_reg_offset 602 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); sram_data_reg_offset 608 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); sram_data_reg_offset 615 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); sram_data_reg_offset 618 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10; sram_data_reg_offset 626 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); sram_data_reg_offset 629 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10; sram_data_reg_offset 396 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c unsigned int *sram_data_reg_offset, sram_data_reg_offset 407 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = 0; sram_data_reg_offset 414 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); sram_data_reg_offset 420 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); sram_data_reg_offset 426 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); sram_data_reg_offset 432 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); sram_data_reg_offset 438 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); sram_data_reg_offset 444 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); sram_data_reg_offset 450 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); sram_data_reg_offset 474 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c unsigned int *sram_data_reg_offset, sram_data_reg_offset 485 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = 0; sram_data_reg_offset 492 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); sram_data_reg_offset 498 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); sram_data_reg_offset 504 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); sram_data_reg_offset 510 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); sram_data_reg_offset 516 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); sram_data_reg_offset 522 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); sram_data_reg_offset 528 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);