sram_addr_reg_offset  241 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
sram_addr_reg_offset  252 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = 0;
sram_addr_reg_offset  259 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
sram_addr_reg_offset  265 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
sram_addr_reg_offset  271 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
sram_addr_reg_offset  277 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
sram_addr_reg_offset  283 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
sram_addr_reg_offset  289 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
sram_addr_reg_offset  295 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
sram_addr_reg_offset  303 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = ;
sram_addr_reg_offset  308 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = ;
sram_addr_reg_offset  313 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = ;
sram_addr_reg_offset  565 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
sram_addr_reg_offset  576 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = 0;
sram_addr_reg_offset  583 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
sram_addr_reg_offset  589 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
sram_addr_reg_offset  595 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
sram_addr_reg_offset  601 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
sram_addr_reg_offset  607 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
sram_addr_reg_offset  614 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 			*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
sram_addr_reg_offset  617 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 			*sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10;
sram_addr_reg_offset  625 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 			*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
sram_addr_reg_offset  628 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 			*sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10;
sram_addr_reg_offset  637 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = ;
sram_addr_reg_offset  642 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = ;
sram_addr_reg_offset  647 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = ;
sram_addr_reg_offset  395 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
sram_addr_reg_offset  406 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = 0;
sram_addr_reg_offset  413 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
sram_addr_reg_offset  419 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
sram_addr_reg_offset  425 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
sram_addr_reg_offset  431 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
sram_addr_reg_offset  437 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
sram_addr_reg_offset  443 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
sram_addr_reg_offset  449 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
sram_addr_reg_offset  457 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = ;
sram_addr_reg_offset  462 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = ;
sram_addr_reg_offset  467 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = ;
sram_addr_reg_offset  473 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
sram_addr_reg_offset  484 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = 0;
sram_addr_reg_offset  491 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
sram_addr_reg_offset  497 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
sram_addr_reg_offset  503 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
sram_addr_reg_offset  509 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
sram_addr_reg_offset  515 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
sram_addr_reg_offset  521 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
sram_addr_reg_offset  527 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
sram_addr_reg_offset  535 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = ;
sram_addr_reg_offset  540 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = ;
sram_addr_reg_offset  545 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = ;