sr_enter           57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
sr_enter           67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
sr_enter           77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
sr_enter           87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
sr_enter          117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		DTN_INFO_MICRO_SEC(s->sr_enter);
sr_enter           99 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 			(s->sr_enter * frac) / ref_clk_mhz / frac, (s->sr_enter * frac) / ref_clk_mhz % frac,
sr_enter          491 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
sr_enter          502 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
sr_enter          513 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
sr_enter          524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
sr_enter          526 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, &s->sr_enter);
sr_enter          540 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, &s->sr_enter);
sr_enter          554 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, &s->sr_enter);
sr_enter          568 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, &s->sr_enter);
sr_enter           46 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h 	uint32_t sr_enter;