sr1 70 arch/parisc/include/asm/asmregs.h sr1: .reg %sr1 sr1 417 arch/parisc/include/asm/assembly.h SAVE_SP (%sr1, PT_SR1 (\regs)) sr1 456 arch/parisc/include/asm/assembly.h REST_SP (%sr1, PT_SR1 (\regs)) sr1 44 arch/parisc/include/asm/kgdb.h unsigned long sr1; sr1 72 arch/parisc/kernel/kgdb.c gr->sr1 = regs->sr[1]; sr1 103 arch/parisc/kernel/kgdb.c regs->sr[1] = gr->sr1; sr1 31 arch/powerpc/include/asm/spu_priv1.h void (*mfc_sr1_set) (struct spu *spu, u64 sr1); sr1 111 arch/powerpc/include/asm/spu_priv1.h spu_mfc_sr1_set (struct spu *spu, u64 sr1) sr1 113 arch/powerpc/include/asm/spu_priv1.h spu_priv1_ops->mfc_sr1_set(spu, sr1); sr1 101 arch/powerpc/platforms/cell/spu_priv1_mmio.c static void mfc_sr1_set(struct spu *spu, u64 sr1) sr1 103 arch/powerpc/platforms/cell/spu_priv1_mmio.c out_be64(&spu->priv1->mfc_sr1_RW, sr1); sr1 298 arch/powerpc/platforms/cell/spufs/backing_ops.c u64 sr1; sr1 301 arch/powerpc/platforms/cell/spufs/backing_ops.c sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK; sr1 302 arch/powerpc/platforms/cell/spufs/backing_ops.c csa->priv1.mfc_sr1_RW = sr1; sr1 309 arch/powerpc/platforms/cell/spufs/backing_ops.c u64 sr1; sr1 312 arch/powerpc/platforms/cell/spufs/backing_ops.c sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; sr1 313 arch/powerpc/platforms/cell/spufs/backing_ops.c csa->priv1.mfc_sr1_RW = sr1; sr1 228 arch/powerpc/platforms/cell/spufs/hw_ops.c u64 sr1; sr1 231 arch/powerpc/platforms/cell/spufs/hw_ops.c sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK; sr1 232 arch/powerpc/platforms/cell/spufs/hw_ops.c spu_mfc_sr1_set(spu, sr1); sr1 239 arch/powerpc/platforms/cell/spufs/hw_ops.c u64 sr1; sr1 242 arch/powerpc/platforms/cell/spufs/hw_ops.c sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; sr1 243 arch/powerpc/platforms/cell/spufs/hw_ops.c spu_mfc_sr1_set(spu, sr1); sr1 86 arch/powerpc/platforms/cell/spufs/run.c u64 sr1; sr1 125 arch/powerpc/platforms/cell/spufs/run.c sr1 = spu_mfc_sr1_get(ctx->spu); sr1 126 arch/powerpc/platforms/cell/spufs/run.c sr1 &= ~MFC_STATE1_PROBLEM_STATE_MASK; sr1 127 arch/powerpc/platforms/cell/spufs/run.c spu_mfc_sr1_set(ctx->spu, sr1); sr1 169 arch/powerpc/platforms/cell/spufs/run.c sr1 |= MFC_STATE1_PROBLEM_STATE_MASK; sr1 170 arch/powerpc/platforms/cell/spufs/run.c spu_mfc_sr1_set(ctx->spu, sr1); sr1 90 arch/powerpc/platforms/ps3/spu.c u64 sr1; sr1 351 arch/powerpc/platforms/ps3/spu.c spu_pdata(spu)->cache.sr1 = 0x33; sr1 532 arch/powerpc/platforms/ps3/spu.c static void mfc_sr1_set(struct spu *spu, u64 sr1) sr1 539 arch/powerpc/platforms/ps3/spu.c BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed)); sr1 541 arch/powerpc/platforms/ps3/spu.c spu_pdata(spu)->cache.sr1 = sr1; sr1 545 arch/powerpc/platforms/ps3/spu.c spu_pdata(spu)->cache.sr1); sr1 550 arch/powerpc/platforms/ps3/spu.c return spu_pdata(spu)->cache.sr1; sr1 25 drivers/gpu/drm/gma500/cdv_device.c u8 sr1; sr1 31 drivers/gpu/drm/gma500/cdv_device.c sr1 = inb(VGA_SR_DATA); sr1 32 drivers/gpu/drm/gma500/cdv_device.c outb(sr1 | 1<<5, VGA_SR_DATA); sr1 15947 drivers/gpu/drm/i915/display/intel_display.c u8 sr1; sr1 15953 drivers/gpu/drm/i915/display/intel_display.c sr1 = inb(VGA_SR_DATA); sr1 15954 drivers/gpu/drm/i915/display/intel_display.c outb(sr1 | 1<<5, VGA_SR_DATA); sr1 75 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c u8 sr1[2]; sr1 85 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c sr1[i] = nvkm_rd08(device, 0x0c03c5 + (i * 0x2000)); sr1 86 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c if (!(sr1[i] & 0x20)) sr1 112 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20); sr1 172 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i]); sr1 1394 drivers/mtd/devices/st_spi_fsm.c uint8_t sr1, cr1, dyb; sr1 1462 drivers/mtd/devices/st_spi_fsm.c stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1); sr1 1463 drivers/mtd/devices/st_spi_fsm.c sta_wr = ((uint16_t)cr1 << 8) | sr1; sr1 1479 drivers/mtd/devices/st_spi_fsm.c uint8_t sr1, sr2; sr1 1506 drivers/mtd/devices/st_spi_fsm.c stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1); sr1 1507 drivers/mtd/devices/st_spi_fsm.c sr_wr = ((uint16_t)sr2 << 8) | sr1; sr1 784 drivers/tty/serial/fsl_lpuart.c unsigned char sr1 = readb(port->membase + UARTSR1); sr1 790 drivers/tty/serial/fsl_lpuart.c if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) sr1 594 drivers/usb/misc/sisusbvga/sisusb_con.c u8 sr1, cr17, pmreg, cr63; sr1 628 drivers/usb/misc/sisusbvga/sisusb_con.c sr1 = 0x00; sr1 636 drivers/usb/misc/sisusbvga/sisusb_con.c sr1 = 0x20; sr1 642 drivers/usb/misc/sisusbvga/sisusb_con.c sr1 = 0x20; sr1 648 drivers/usb/misc/sisusbvga/sisusb_con.c sr1 = 0x20; sr1 658 drivers/usb/misc/sisusbvga/sisusb_con.c sisusb_setidxregandor(sisusb, SISSR, 0x01, ~0x20, sr1); sr1 1665 include/linux/platform_data/cros_ec_commands.h uint8_t sr1, sr2; sr1 172 kernel/locking/lockdep_proc.c sr1 = debug_atomic_read(redundant_softirqs_on), sr1 196 kernel/locking/lockdep_proc.c seq_printf(m, " redundant softirq ons: %11llu\n", sr1);