sqr 132 drivers/iio/adc/stm32-adc.c const struct stm32_adc_regs *sqr; sqr 341 drivers/iio/adc/stm32-adc.c .sqr = stm32f4_sq, sqr 433 drivers/iio/adc/stm32-adc.c .sqr = stm32h7_sq, sqr 955 drivers/iio/adc/stm32-adc.c const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; sqr 977 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, sqr[i].reg); sqr 978 drivers/iio/adc/stm32-adc.c val &= ~sqr[i].mask; sqr 979 drivers/iio/adc/stm32-adc.c val |= chan->channel << sqr[i].shift; sqr 980 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, sqr[i].reg, val); sqr 987 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, sqr[0].reg); sqr 988 drivers/iio/adc/stm32-adc.c val &= ~sqr[0].mask; sqr 989 drivers/iio/adc/stm32-adc.c val |= ((i - 1) << sqr[0].shift); sqr 990 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, sqr[0].reg, val); sqr 1129 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, regs->sqr[1].reg); sqr 1130 drivers/iio/adc/stm32-adc.c val &= ~regs->sqr[1].mask; sqr 1131 drivers/iio/adc/stm32-adc.c val |= chan->channel << regs->sqr[1].shift; sqr 1132 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, regs->sqr[1].reg, val); sqr 1135 drivers/iio/adc/stm32-adc.c stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask);