spxx_trn4_ctl     202 arch/mips/cavium-octeon/executive/cvmx-spi.c 	union cvmx_spxx_trn4_ctl spxx_trn4_ctl;
spxx_trn4_ctl     278 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_trn4_ctl.s.trntest = 0;
spxx_trn4_ctl     279 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_trn4_ctl.s.jitter = 1;
spxx_trn4_ctl     280 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_trn4_ctl.s.clr_boot = 1;
spxx_trn4_ctl     281 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_trn4_ctl.s.set_boot = 0;
spxx_trn4_ctl     283 arch/mips/cavium-octeon/executive/cvmx-spi.c 		spxx_trn4_ctl.s.maxdist = 3;
spxx_trn4_ctl     285 arch/mips/cavium-octeon/executive/cvmx-spi.c 		spxx_trn4_ctl.s.maxdist = 8;
spxx_trn4_ctl     286 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_trn4_ctl.s.macro_en = 1;
spxx_trn4_ctl     287 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_trn4_ctl.s.mux_en = 1;
spxx_trn4_ctl     288 arch/mips/cavium-octeon/executive/cvmx-spi.c 	cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);
spxx_trn4_ctl     510 arch/mips/cavium-octeon/executive/cvmx-spi.c 	union cvmx_spxx_trn4_ctl spxx_trn4_ctl;
spxx_trn4_ctl     533 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface));
spxx_trn4_ctl     534 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_trn4_ctl.s.clr_boot = 1;
spxx_trn4_ctl     535 arch/mips/cavium-octeon/executive/cvmx-spi.c 	cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);