spxx_clk_ctl      198 arch/mips/cavium-octeon/executive/cvmx-spi.c 	union cvmx_spxx_clk_ctl spxx_clk_ctl;
spxx_clk_ctl      215 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.u64 = 0;
spxx_clk_ctl      216 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.runbist = 1;
spxx_clk_ctl      217 arch/mips/cavium-octeon/executive/cvmx-spi.c 	cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
spxx_clk_ctl      256 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.u64 = 0;
spxx_clk_ctl      257 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.seetrn = 0;
spxx_clk_ctl      258 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.clkdly = 0x10;
spxx_clk_ctl      259 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.runbist = 0;
spxx_clk_ctl      260 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.statdrv = 0;
spxx_clk_ctl      262 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.statrcv = 1;
spxx_clk_ctl      263 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.sndtrn = 0;
spxx_clk_ctl      264 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.drptrn = 0;
spxx_clk_ctl      265 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.rcvtrn = 0;
spxx_clk_ctl      266 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.srxdlck = 0;
spxx_clk_ctl      267 arch/mips/cavium-octeon/executive/cvmx-spi.c 	cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
spxx_clk_ctl      271 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.srxdlck = 1;
spxx_clk_ctl      272 arch/mips/cavium-octeon/executive/cvmx-spi.c 	cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
spxx_clk_ctl      517 arch/mips/cavium-octeon/executive/cvmx-spi.c 	union cvmx_spxx_clk_ctl spxx_clk_ctl;
spxx_clk_ctl      518 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.u64 = 0;
spxx_clk_ctl      519 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.seetrn = 0;
spxx_clk_ctl      520 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.clkdly = 0x10;
spxx_clk_ctl      521 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.runbist = 0;
spxx_clk_ctl      522 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.statdrv = 0;
spxx_clk_ctl      524 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.statrcv = 1;
spxx_clk_ctl      525 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.sndtrn = 1;
spxx_clk_ctl      526 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.drptrn = 1;
spxx_clk_ctl      527 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.rcvtrn = 1;
spxx_clk_ctl      528 arch/mips/cavium-octeon/executive/cvmx-spi.c 	spxx_clk_ctl.s.srxdlck = 1;
spxx_clk_ctl      529 arch/mips/cavium-octeon/executive/cvmx-spi.c 	cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);