spx_int_msk       305 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 	union cvmx_spxx_int_msk spx_int_msk;
spx_int_msk       308 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 	spx_int_msk.u64 = 0;
spx_int_msk       311 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.calerr = 1;
spx_int_msk       312 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.syncerr = 1;
spx_int_msk       313 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.diperr = 1;
spx_int_msk       314 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.tpaovr = 1;
spx_int_msk       315 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.rsverr = 1;
spx_int_msk       316 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.drwnng = 1;
spx_int_msk       317 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.clserr = 1;
spx_int_msk       318 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.spiovr = 1;
spx_int_msk       320 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.abnorm = 1;
spx_int_msk       321 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.prtnxa = 1;
spx_int_msk       325 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.calerr = 1;
spx_int_msk       326 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.syncerr = 1;
spx_int_msk       327 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.diperr = 1;
spx_int_msk       328 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.tpaovr = 1;
spx_int_msk       329 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.rsverr = 1;
spx_int_msk       330 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.drwnng = 1;
spx_int_msk       331 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.clserr = 1;
spx_int_msk       332 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.spiovr = 1;
spx_int_msk       334 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.abnorm = 1;
spx_int_msk       335 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		spx_int_msk.s.prtnxa = 1;
spx_int_msk       337 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 	cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64);