spu_adv_reg       270 drivers/gpu/drm/armada/armada_crtc.c 		val |= dcrtc->v[i].spu_adv_reg;
spu_adv_reg       363 drivers/gpu/drm/armada/armada_crtc.c 	dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;
spu_adv_reg       368 drivers/gpu/drm/armada/armada_crtc.c 		dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;
spu_adv_reg       385 drivers/gpu/drm/armada/armada_crtc.c 		armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
spu_adv_reg        46 drivers/gpu/drm/armada/armada_crtc.h 		uint32_t	spu_adv_reg;