sprstate 2766 drivers/gpu/drm/i915/intel_pm.c const struct intel_plane_state *sprstate, sprstate 2787 drivers/gpu/drm/i915/intel_pm.c if (sprstate) sprstate 2788 drivers/gpu/drm/i915/intel_pm.c result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency); sprstate 3123 drivers/gpu/drm/i915/intel_pm.c const struct intel_plane_state *sprstate = NULL; sprstate 3136 drivers/gpu/drm/i915/intel_pm.c sprstate = ps; sprstate 3142 drivers/gpu/drm/i915/intel_pm.c if (sprstate) { sprstate 3143 drivers/gpu/drm/i915/intel_pm.c pipe_wm->sprites_enabled = sprstate->base.visible; sprstate 3144 drivers/gpu/drm/i915/intel_pm.c pipe_wm->sprites_scaled = sprstate->base.visible && sprstate 3145 drivers/gpu/drm/i915/intel_pm.c (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 || sprstate 3146 drivers/gpu/drm/i915/intel_pm.c drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16); sprstate 3161 drivers/gpu/drm/i915/intel_pm.c pristate, sprstate, curstate, &pipe_wm->wm[0]); sprstate 3175 drivers/gpu/drm/i915/intel_pm.c pristate, sprstate, curstate, wm);