spll_func_cntl_3 4959 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
spll_func_cntl_3 5066 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		cpu_to_be32(spll_func_cntl_3);
spll_func_cntl_3 5253 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
spll_func_cntl_3 5281 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
spll_func_cntl_3 5282 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
spll_func_cntl_3 5283 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	spll_func_cntl_3 |= SPLL_DITHEN;
spll_func_cntl_3 5306 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
spll_func_cntl_3  301 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
spll_func_cntl_3  331 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
spll_func_cntl_3  335 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
spll_func_cntl_3  360 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
spll_func_cntl_3  863 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
spll_func_cntl_3  893 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
spll_func_cntl_3  897 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
spll_func_cntl_3  929 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
spll_func_cntl_3  801 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
spll_func_cntl_3  831 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
spll_func_cntl_3  835 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
spll_func_cntl_3  864 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
spll_func_cntl_3  544 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
spll_func_cntl_3  574 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
spll_func_cntl_3  578 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
spll_func_cntl_3  607 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
spll_func_cntl_3 3165 drivers/gpu/drm/radeon/ci_dpm.c 	u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
spll_func_cntl_3 3183 drivers/gpu/drm/radeon/ci_dpm.c 	spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
spll_func_cntl_3 3184 drivers/gpu/drm/radeon/ci_dpm.c 	spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
spll_func_cntl_3 3185 drivers/gpu/drm/radeon/ci_dpm.c 	spll_func_cntl_3 |= SPLL_DITHEN;
spll_func_cntl_3 3206 drivers/gpu/drm/radeon/ci_dpm.c 	sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
spll_func_cntl_3 1348 drivers/gpu/drm/radeon/cypress_dpm.c 	u32 spll_func_cntl_3 =
spll_func_cntl_3 1453 drivers/gpu/drm/radeon/cypress_dpm.c 		cpu_to_be32(spll_func_cntl_3);
spll_func_cntl_3 1804 drivers/gpu/drm/radeon/ni_dpm.c 	u32 spll_func_cntl_3    = ni_pi->clock_registers.cg_spll_func_cntl_3;
spll_func_cntl_3 1916 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
spll_func_cntl_3 2007 drivers/gpu/drm/radeon/ni_dpm.c 	u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;
spll_func_cntl_3 2036 drivers/gpu/drm/radeon/ni_dpm.c 	spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
spll_func_cntl_3 2037 drivers/gpu/drm/radeon/ni_dpm.c 	spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
spll_func_cntl_3 2038 drivers/gpu/drm/radeon/ni_dpm.c 	spll_func_cntl_3 |= SPLL_DITHEN;
spll_func_cntl_3 2061 drivers/gpu/drm/radeon/ni_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
spll_func_cntl_3   47 drivers/gpu/drm/radeon/rv730_dpm.c 	u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
spll_func_cntl_3   86 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
spll_func_cntl_3   87 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
spll_func_cntl_3   88 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl_3 |= SPLL_DITHEN;
spll_func_cntl_3  111 drivers/gpu/drm/radeon/rv730_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
spll_func_cntl_3  239 drivers/gpu/drm/radeon/rv730_dpm.c 	u32 spll_func_cntl_3;
spll_func_cntl_3  288 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
spll_func_cntl_3  306 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
spll_func_cntl_3  127 drivers/gpu/drm/radeon/rv740_dpm.c 	u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;
spll_func_cntl_3  154 drivers/gpu/drm/radeon/rv740_dpm.c 	spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
spll_func_cntl_3  155 drivers/gpu/drm/radeon/rv740_dpm.c 	spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
spll_func_cntl_3  156 drivers/gpu/drm/radeon/rv740_dpm.c 	spll_func_cntl_3 |= SPLL_DITHEN;
spll_func_cntl_3  179 drivers/gpu/drm/radeon/rv740_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
spll_func_cntl_3  324 drivers/gpu/drm/radeon/rv740_dpm.c 	u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;
spll_func_cntl_3  384 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
spll_func_cntl_3  493 drivers/gpu/drm/radeon/rv770_dpm.c 	u32 spll_func_cntl_3 =
spll_func_cntl_3  533 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
spll_func_cntl_3  534 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
spll_func_cntl_3  535 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl_3 |= SPLL_DITHEN;
spll_func_cntl_3  558 drivers/gpu/drm/radeon/rv770_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
spll_func_cntl_3  931 drivers/gpu/drm/radeon/rv770_dpm.c 	u32 spll_func_cntl_3 =
spll_func_cntl_3  993 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
spll_func_cntl_3 4497 drivers/gpu/drm/radeon/si_dpm.c 	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
spll_func_cntl_3 4603 drivers/gpu/drm/radeon/si_dpm.c 		cpu_to_be32(spll_func_cntl_3);
spll_func_cntl_3 4791 drivers/gpu/drm/radeon/si_dpm.c 	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
spll_func_cntl_3 4819 drivers/gpu/drm/radeon/si_dpm.c 	spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
spll_func_cntl_3 4820 drivers/gpu/drm/radeon/si_dpm.c 	spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
spll_func_cntl_3 4821 drivers/gpu/drm/radeon/si_dpm.c 	spll_func_cntl_3 |= SPLL_DITHEN;
spll_func_cntl_3 4844 drivers/gpu/drm/radeon/si_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;