spll_func_cntl_2 4958 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
spll_func_cntl_2 5039 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2 5040 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(4);
spll_func_cntl_2 5064 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		cpu_to_be32(spll_func_cntl_2);
spll_func_cntl_2 5252 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
spll_func_cntl_2 5278 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2 5279 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(2);
spll_func_cntl_2 5305 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
spll_func_cntl_2 1384 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
spll_func_cntl_2 1417 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	spll_func_cntl_2    = PHM_SET_FIELD(spll_func_cntl_2,
spll_func_cntl_2 1421 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
spll_func_cntl_2 1312 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
spll_func_cntl_2 1351 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
spll_func_cntl_2 1355 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
spll_func_cntl_2 1432 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
spll_func_cntl_2 1465 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	spll_func_cntl_2    = PHM_SET_FIELD(spll_func_cntl_2,
spll_func_cntl_2 1469 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
spll_func_cntl_2 1184 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
spll_func_cntl_2 1214 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
spll_func_cntl_2 1218 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
spll_func_cntl_2 2996 drivers/gpu/drm/radeon/ci_dpm.c 	u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
spll_func_cntl_2 3025 drivers/gpu/drm/radeon/ci_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2 3026 drivers/gpu/drm/radeon/ci_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(4);
spll_func_cntl_2 3029 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
spll_func_cntl_2 1346 drivers/gpu/drm/radeon/cypress_dpm.c 	u32 spll_func_cntl_2 =
spll_func_cntl_2 1431 drivers/gpu/drm/radeon/cypress_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2 1432 drivers/gpu/drm/radeon/cypress_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(4);
spll_func_cntl_2 1451 drivers/gpu/drm/radeon/cypress_dpm.c 		cpu_to_be32(spll_func_cntl_2);
spll_func_cntl_2 1803 drivers/gpu/drm/radeon/ni_dpm.c 	u32 spll_func_cntl_2    = ni_pi->clock_registers.cg_spll_func_cntl_2;
spll_func_cntl_2 1902 drivers/gpu/drm/radeon/ni_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2 1903 drivers/gpu/drm/radeon/ni_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(4);
spll_func_cntl_2 1915 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
spll_func_cntl_2 2006 drivers/gpu/drm/radeon/ni_dpm.c 	u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;
spll_func_cntl_2 2033 drivers/gpu/drm/radeon/ni_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2 2034 drivers/gpu/drm/radeon/ni_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(2);
spll_func_cntl_2 2060 drivers/gpu/drm/radeon/ni_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
spll_func_cntl_2   46 drivers/gpu/drm/radeon/rv730_dpm.c 	u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
spll_func_cntl_2   83 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2   84 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(2);
spll_func_cntl_2  110 drivers/gpu/drm/radeon/rv730_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
spll_func_cntl_2  238 drivers/gpu/drm/radeon/rv730_dpm.c 	u32 spll_func_cntl_2;
spll_func_cntl_2  287 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
spll_func_cntl_2  293 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2  294 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(4);
spll_func_cntl_2  305 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
spll_func_cntl_2  126 drivers/gpu/drm/radeon/rv740_dpm.c 	u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;
spll_func_cntl_2  151 drivers/gpu/drm/radeon/rv740_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2  152 drivers/gpu/drm/radeon/rv740_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(2);
spll_func_cntl_2  178 drivers/gpu/drm/radeon/rv740_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
spll_func_cntl_2  323 drivers/gpu/drm/radeon/rv740_dpm.c 	u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;
spll_func_cntl_2  370 drivers/gpu/drm/radeon/rv740_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2  371 drivers/gpu/drm/radeon/rv740_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(4);
spll_func_cntl_2  383 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
spll_func_cntl_2  491 drivers/gpu/drm/radeon/rv770_dpm.c 	u32 spll_func_cntl_2 =
spll_func_cntl_2  530 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2  531 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(2);
spll_func_cntl_2  557 drivers/gpu/drm/radeon/rv770_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
spll_func_cntl_2  929 drivers/gpu/drm/radeon/rv770_dpm.c 	u32 spll_func_cntl_2 =
spll_func_cntl_2  978 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2  979 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(4);
spll_func_cntl_2  992 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
spll_func_cntl_2 4496 drivers/gpu/drm/radeon/si_dpm.c 	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
spll_func_cntl_2 4576 drivers/gpu/drm/radeon/si_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2 4577 drivers/gpu/drm/radeon/si_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(4);
spll_func_cntl_2 4601 drivers/gpu/drm/radeon/si_dpm.c 		cpu_to_be32(spll_func_cntl_2);
spll_func_cntl_2 4790 drivers/gpu/drm/radeon/si_dpm.c 	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
spll_func_cntl_2 4816 drivers/gpu/drm/radeon/si_dpm.c 	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
spll_func_cntl_2 4817 drivers/gpu/drm/radeon/si_dpm.c 	spll_func_cntl_2 |= SCLK_MUX_SEL(2);
spll_func_cntl_2 4843 drivers/gpu/drm/radeon/si_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;