spll_func_cntl   4957 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
spll_func_cntl   5062 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		cpu_to_be32(spll_func_cntl);
spll_func_cntl   5251 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
spll_func_cntl   5274 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
spll_func_cntl   5275 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
spll_func_cntl   5276 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
spll_func_cntl   5304 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
spll_func_cntl    300 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
spll_func_cntl    325 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
spll_func_cntl    327 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
spll_func_cntl   1383 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
spll_func_cntl   1413 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
spll_func_cntl   1415 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
spll_func_cntl   1420 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
spll_func_cntl    862 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
spll_func_cntl    887 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
spll_func_cntl    889 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
spll_func_cntl   1311 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
spll_func_cntl   1347 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
spll_func_cntl   1349 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
spll_func_cntl   1354 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
spll_func_cntl    800 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
spll_func_cntl    825 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
spll_func_cntl    827 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
spll_func_cntl   1431 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
spll_func_cntl   1461 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
spll_func_cntl   1463 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
spll_func_cntl   1468 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
spll_func_cntl    543 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
spll_func_cntl    568 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
spll_func_cntl    570 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
spll_func_cntl   1183 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
spll_func_cntl   1210 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
spll_func_cntl   1212 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
spll_func_cntl   1217 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
spll_func_cntl   2995 drivers/gpu/drm/radeon/ci_dpm.c 	u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
spll_func_cntl   3022 drivers/gpu/drm/radeon/ci_dpm.c 	spll_func_cntl &= ~SPLL_PWRON;
spll_func_cntl   3023 drivers/gpu/drm/radeon/ci_dpm.c 	spll_func_cntl |= SPLL_RESET;
spll_func_cntl   3028 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
spll_func_cntl   1344 drivers/gpu/drm/radeon/cypress_dpm.c 	u32 spll_func_cntl =
spll_func_cntl   1429 drivers/gpu/drm/radeon/cypress_dpm.c 		spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
spll_func_cntl   1449 drivers/gpu/drm/radeon/cypress_dpm.c 		cpu_to_be32(spll_func_cntl);
spll_func_cntl   1802 drivers/gpu/drm/radeon/ni_dpm.c 	u32 spll_func_cntl      = ni_pi->clock_registers.cg_spll_func_cntl;
spll_func_cntl   1914 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
spll_func_cntl   2005 drivers/gpu/drm/radeon/ni_dpm.c 	u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;
spll_func_cntl   2029 drivers/gpu/drm/radeon/ni_dpm.c 	spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
spll_func_cntl   2030 drivers/gpu/drm/radeon/ni_dpm.c 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
spll_func_cntl   2031 drivers/gpu/drm/radeon/ni_dpm.c 	spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
spll_func_cntl   2059 drivers/gpu/drm/radeon/ni_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
spll_func_cntl     45 drivers/gpu/drm/radeon/rv730_dpm.c 	u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
spll_func_cntl     75 drivers/gpu/drm/radeon/rv730_dpm.c 		spll_func_cntl |= SPLL_DIVEN;
spll_func_cntl     77 drivers/gpu/drm/radeon/rv730_dpm.c 		spll_func_cntl &= ~SPLL_DIVEN;
spll_func_cntl     78 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK);
spll_func_cntl     79 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
spll_func_cntl     80 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
spll_func_cntl     81 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);
spll_func_cntl    109 drivers/gpu/drm/radeon/rv730_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
spll_func_cntl    237 drivers/gpu/drm/radeon/rv730_dpm.c 	u32 spll_func_cntl;
spll_func_cntl    286 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
spll_func_cntl    290 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl |= SPLL_RESET | SPLL_BYPASS_EN;
spll_func_cntl    291 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl &= ~SPLL_SLEEP;
spll_func_cntl    304 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
spll_func_cntl    125 drivers/gpu/drm/radeon/rv740_dpm.c 	u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;
spll_func_cntl    147 drivers/gpu/drm/radeon/rv740_dpm.c 	spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
spll_func_cntl    148 drivers/gpu/drm/radeon/rv740_dpm.c 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
spll_func_cntl    149 drivers/gpu/drm/radeon/rv740_dpm.c 	spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
spll_func_cntl    177 drivers/gpu/drm/radeon/rv740_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
spll_func_cntl    322 drivers/gpu/drm/radeon/rv740_dpm.c 	u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;
spll_func_cntl    368 drivers/gpu/drm/radeon/rv740_dpm.c 	spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
spll_func_cntl    382 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
spll_func_cntl    489 drivers/gpu/drm/radeon/rv770_dpm.c 	u32 spll_func_cntl =
spll_func_cntl    522 drivers/gpu/drm/radeon/rv770_dpm.c 		spll_func_cntl |= SPLL_DIVEN;
spll_func_cntl    524 drivers/gpu/drm/radeon/rv770_dpm.c 		spll_func_cntl &= ~SPLL_DIVEN;
spll_func_cntl    525 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK);
spll_func_cntl    526 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
spll_func_cntl    527 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
spll_func_cntl    528 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);
spll_func_cntl    556 drivers/gpu/drm/radeon/rv770_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
spll_func_cntl    927 drivers/gpu/drm/radeon/rv770_dpm.c 	u32 spll_func_cntl =
spll_func_cntl    976 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
spll_func_cntl    991 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
spll_func_cntl   4495 drivers/gpu/drm/radeon/si_dpm.c 	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
spll_func_cntl   4599 drivers/gpu/drm/radeon/si_dpm.c 		cpu_to_be32(spll_func_cntl);
spll_func_cntl   4789 drivers/gpu/drm/radeon/si_dpm.c 	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
spll_func_cntl   4812 drivers/gpu/drm/radeon/si_dpm.c 	spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
spll_func_cntl   4813 drivers/gpu/drm/radeon/si_dpm.c 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
spll_func_cntl   4814 drivers/gpu/drm/radeon/si_dpm.c 	spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
spll_func_cntl   4842 drivers/gpu/drm/radeon/si_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;