sp1_base           55 arch/parisc/include/asm/superio.h 	u32 sp1_base;
sp1_base          171 drivers/parisc/superio.c 	pci_read_config_dword (pdev, SIO_SP1BAR, &sio->sp1_base);
sp1_base          172 drivers/parisc/superio.c 	sio->sp1_base &= ~1;
sp1_base          173 drivers/parisc/superio.c 	printk(KERN_INFO PFX "Serial port 1 at 0x%x\n", sio->sp1_base);
sp1_base          398 drivers/parisc/superio.c 	serial_port.iobase	= sio_dev.sp1_base;