source_vcpu 94 virt/kvm/arm/psci.c static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) source_vcpu 97 virt/kvm/arm/psci.c struct kvm *kvm = source_vcpu->kvm; source_vcpu 101 virt/kvm/arm/psci.c cpu_id = smccc_get_arg1(source_vcpu) & MPIDR_HWID_BITMASK; source_vcpu 102 virt/kvm/arm/psci.c if (vcpu_mode_is_32bit(source_vcpu)) source_vcpu 114 virt/kvm/arm/psci.c if (kvm_psci_version(source_vcpu, kvm) != KVM_ARM_PSCI_0_1) source_vcpu 122 virt/kvm/arm/psci.c reset_state->pc = smccc_get_arg2(source_vcpu); source_vcpu 125 virt/kvm/arm/psci.c reset_state->be = kvm_vcpu_is_be(source_vcpu); source_vcpu 131 virt/kvm/arm/psci.c reset_state->r0 = smccc_get_arg3(source_vcpu); source_vcpu 108 virt/kvm/arm/vgic/vgic-mmio-v2.c static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu, source_vcpu 112 virt/kvm/arm/vgic/vgic-mmio-v2.c int nr_vcpus = atomic_read(&source_vcpu->kvm->online_vcpus); source_vcpu 125 virt/kvm/arm/vgic/vgic-mmio-v2.c targets &= ~(1U << source_vcpu->vcpu_id); /* but self */ source_vcpu 128 virt/kvm/arm/vgic/vgic-mmio-v2.c targets = (1U << source_vcpu->vcpu_id); source_vcpu 134 virt/kvm/arm/vgic/vgic-mmio-v2.c kvm_for_each_vcpu(c, vcpu, source_vcpu->kvm) { source_vcpu 140 virt/kvm/arm/vgic/vgic-mmio-v2.c irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid); source_vcpu 144 virt/kvm/arm/vgic/vgic-mmio-v2.c irq->source |= 1U << source_vcpu->vcpu_id; source_vcpu 146 virt/kvm/arm/vgic/vgic-mmio-v2.c vgic_queue_irq_unlock(source_vcpu->kvm, irq, flags); source_vcpu 147 virt/kvm/arm/vgic/vgic-mmio-v2.c vgic_put_irq(source_vcpu->kvm, irq);