source_scan        45 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			if (v->source_scan[k] == dcn_bw_hor) {
source_scan        55 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			if (v->source_scan[k] == dcn_bw_hor) {
source_scan       140 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		if ((v->source_surface_mode[k] == dcn_bw_sw_linear && v->source_scan[k] != dcn_bw_hor) || ((v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_var_d || v->source_surface_mode[k] == dcn_bw_sw_var_d_x) && v->source_pixel_format[k] != dcn_bw_rgb_sub_64)) {
source_scan       147 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		if (v->source_scan[k] == dcn_bw_hor) {
source_scan       180 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		if (v->pte_enable == dcn_bw_yes && v->source_scan[k] != dcn_bw_hor && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x)) {
source_scan       183 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor && (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32) && (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) {
source_scan       374 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		if (v->source_scan[k] == dcn_bw_hor) {
source_scan       383 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) {
source_scan       396 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) {
source_scan       405 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) {
source_scan       629 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 					if (v->source_scan[k] == dcn_bw_hor) {
source_scan       667 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 					else if (v->source_scan[k] == dcn_bw_hor) {
source_scan       689 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 						if (v->source_scan[k] == dcn_bw_hor) {
source_scan       728 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 						else if (v->source_scan[k] == dcn_bw_hor) {
source_scan      1091 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		if (v->source_scan[k] == dcn_bw_hor) {
source_scan      1100 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) {
source_scan      1113 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) {
source_scan      1122 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) {
source_scan      1136 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		if (v->source_scan[k] == dcn_bw_hor) {
source_scan      1250 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		if (v->source_scan[k] == dcn_bw_hor) {
source_scan      1480 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			if (v->source_scan[k] == dcn_bw_hor) {
source_scan      1518 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			else if (v->source_scan[k] == dcn_bw_hor) {
source_scan      1539 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 				if (v->source_scan[k] == dcn_bw_hor) {
source_scan      1577 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 				else if (v->source_scan[k] == dcn_bw_hor) {
source_scan       333 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->src.source_scan         = dm_horz;
source_scan       348 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		input->src.source_scan = dm_horz;
source_scan       352 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		input->src.source_scan = dm_vert;
source_scan       911 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			v->source_scan[input_idx] = dcn_bw_hor;
source_scan       997 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
source_scan      1058 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		if (v->source_scan[k] == dcn_bw_hor)
source_scan      2045 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
source_scan      2079 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
source_scan       246 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
source_scan       327 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		unsigned int source_scan,
source_scan       331 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	bool surf_vert = (source_scan == dm_vert);
source_scan       716 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			pipe_src_param.source_scan,
source_scan       963 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
source_scan       246 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
source_scan       327 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		unsigned int source_scan,
source_scan       331 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	bool surf_vert = (source_scan == dm_vert);
source_scan       716 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			pipe_src_param.source_scan,
source_scan       963 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
source_scan       229 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
source_scan       315 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		unsigned int source_scan,
source_scan       320 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	bool surf_vert = (source_scan == dm_vert);
source_scan       708 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
source_scan       757 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			pipe_param.src.source_scan,
source_scan      1015 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
source_scan       225 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	int source_scan;
source_scan       380 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 				(enum scan_direction_class) (src->source_scan);
source_scan       285 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
source_scan       373 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		int source_scan,
source_scan       377 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	bool surf_vert = (source_scan == dm_vert);
source_scan       631 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	surf_vert = (pipe_src_param.source_scan == dm_vert);
source_scan       918 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			pipe_src_param.source_scan,
source_scan      1186 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	access_dir = (e2e_pipe_param.pipe.src.source_scan == dm_vert); /* vp access direction: horizontal or vertical accessed */
source_scan       184 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h 	enum dcn_bw_defs source_scan[number_of_planes_minus_one + 1];