source_max 220 drivers/gpu/drm/i915/display/intel_dp.c int source_max = intel_dig_port->max_lanes; source_max 224 drivers/gpu/drm/i915/display/intel_dp.c return min3(source_max, sink_max, fia_max); source_max 463 drivers/gpu/drm/i915/display/intel_panel.c u32 source_min, u32 source_max, source_max 468 drivers/gpu/drm/i915/display/intel_panel.c WARN_ON(source_min > source_max); source_max 472 drivers/gpu/drm/i915/display/intel_panel.c source_val = clamp(source_val, source_min, source_max); source_max 477 drivers/gpu/drm/i915/display/intel_panel.c target_val = DIV_ROUND_CLOSEST_ULL(target_val, source_max - source_min); source_max 282 drivers/gpu/drm/rockchip/cdn-dp-core.c u32 requested, actual, rate, sink_max, source_max = 0; source_max 303 drivers/gpu/drm/rockchip/cdn-dp-core.c source_max = dp->lanes; source_max 305 drivers/gpu/drm/rockchip/cdn-dp-core.c lanes = min(source_max, sink_max); source_max 307 drivers/gpu/drm/rockchip/cdn-dp-core.c source_max = drm_dp_bw_code_to_link_rate(CDN_DP_MAX_LINK_RATE); source_max 309 drivers/gpu/drm/rockchip/cdn-dp-core.c rate = min(source_max, sink_max);