sosc 961 drivers/clk/microchip/clk-core.c struct pic32_sec_osc *sosc = clkhw_to_sosc(hw); sosc 966 drivers/clk/microchip/clk-core.c writel(sosc->enable_mask, PIC32_SET(sosc->enable_reg)); sosc 969 drivers/clk/microchip/clk-core.c return readl_poll_timeout_atomic(sosc->status_reg, v, sosc 970 drivers/clk/microchip/clk-core.c v & sosc->status_mask, 1, 100); sosc 975 drivers/clk/microchip/clk-core.c struct pic32_sec_osc *sosc = clkhw_to_sosc(hw); sosc 978 drivers/clk/microchip/clk-core.c writel(sosc->enable_mask, PIC32_CLR(sosc->enable_reg)); sosc 983 drivers/clk/microchip/clk-core.c struct pic32_sec_osc *sosc = clkhw_to_sosc(hw); sosc 987 drivers/clk/microchip/clk-core.c enabled = readl(sosc->enable_reg) & sosc->enable_mask; sosc 988 drivers/clk/microchip/clk-core.c ready = readl(sosc->status_reg) & sosc->status_mask; sosc 1009 drivers/clk/microchip/clk-core.c struct pic32_sec_osc *sosc; sosc 1011 drivers/clk/microchip/clk-core.c sosc = devm_kzalloc(core->dev, sizeof(*sosc), GFP_KERNEL); sosc 1012 drivers/clk/microchip/clk-core.c if (!sosc) sosc 1015 drivers/clk/microchip/clk-core.c sosc->core = core; sosc 1016 drivers/clk/microchip/clk-core.c sosc->hw.init = &data->init_data; sosc 1017 drivers/clk/microchip/clk-core.c sosc->fixed_rate = data->fixed_rate; sosc 1018 drivers/clk/microchip/clk-core.c sosc->enable_mask = data->enable_mask; sosc 1019 drivers/clk/microchip/clk-core.c sosc->status_mask = data->status_mask; sosc 1020 drivers/clk/microchip/clk-core.c sosc->enable_reg = data->enable_reg + core->iobase; sosc 1021 drivers/clk/microchip/clk-core.c sosc->status_reg = data->status_reg + core->iobase; sosc 1023 drivers/clk/microchip/clk-core.c return devm_clk_register(core->dev, &sosc->hw);