sor 299 arch/ia64/kernel/unaligned.c rotate_reg (unsigned long sor, unsigned long rrb, unsigned long reg) sor 302 arch/ia64/kernel/unaligned.c if (reg >= sor) sor 303 arch/ia64/kernel/unaligned.c reg -= sor; sor 316 arch/ia64/kernel/unaligned.c long sor = 8 * ((regs->cr_ifs >> 14) & 0xf); sor 326 arch/ia64/kernel/unaligned.c if (ridx < sor) sor 327 arch/ia64/kernel/unaligned.c ridx = rotate_reg(sor, rrb_gr, ridx); sor 389 arch/ia64/kernel/unaligned.c long sor = 8 * ((regs->cr_ifs >> 14) & 0xf); sor 399 arch/ia64/kernel/unaligned.c if (ridx < sor) sor 400 arch/ia64/kernel/unaligned.c ridx = rotate_reg(sor, rrb_gr, ridx); sor 306 arch/powerpc/platforms/8xx/cpm1.c __be32 dir, par, sor, odr, dat; sor 340 arch/powerpc/platforms/8xx/cpm1.c setbits32(&iop->sor, pin); sor 342 arch/powerpc/platforms/8xx/cpm1.c clrbits32(&iop->sor, pin); sor 326 arch/powerpc/sysdev/cpm2.c u32 dir, par, sor, odr, dat; sor 348 arch/powerpc/sysdev/cpm2.c setbits32(&iop[port].sor, pin); sor 350 arch/powerpc/sysdev/cpm2.c clrbits32(&iop[port].sor, pin); sor 95 arch/powerpc/sysdev/cpm_common.c u32 dir, par, sor, odr, dat; sor 25 drivers/gpu/drm/nouveau/dispnv50/core.h } *dac, *pior, *sor; sor 83 drivers/gpu/drm/nouveau/dispnv50/core507d.c .sor = &sor507d, sor 33 drivers/gpu/drm/nouveau/dispnv50/core827d.c .sor = &sor507d, sor 33 drivers/gpu/drm/nouveau/dispnv50/core907d.c .sor = &sor907d, sor 33 drivers/gpu/drm/nouveau/dispnv50/core917d.c .sor = &sor907d, sor 103 drivers/gpu/drm/nouveau/dispnv50/corec37d.c .sor = &sorc37d, sor 54 drivers/gpu/drm/nouveau/dispnv50/corec57d.c .sor = &sorc37d, sor 1423 drivers/gpu/drm/nouveau/dispnv50/disp.c core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); sor 38 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h struct sor_conf sor; sor 47 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h struct sor_conf sor; sor 52 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h struct sor_conf sor; sor 1444 drivers/gpu/drm/nouveau/nouveau_bios.c entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4; sor 1445 drivers/gpu/drm/nouveau/nouveau_bios.c link = entry->lvdsconf.sor.link; sor 1470 drivers/gpu/drm/nouveau/nouveau_bios.c entry->dpconf.sor.link = (conf & 0x00000030) >> 4; sor 1500 drivers/gpu/drm/nouveau/nouveau_bios.c link = entry->dpconf.sor.link; sor 1504 drivers/gpu/drm/nouveau/nouveau_bios.c entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; sor 1506 drivers/gpu/drm/nouveau/nouveau_bios.c link = entry->tmdsconf.sor.link; sor 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c .sor = { .cnt = nv50_sor_cnt, .new = g84_sor_new }, sor 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c .sor = { .cnt = g94_sor_cnt, .new = g94_sor_new }, sor 216 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c for (i = 0; i < disp->sor.nr; i++) { sor 265 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c .sor = { .cnt = gf119_sor_cnt, .new = gf119_sor_new }, sor 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c .sor = { .cnt = gf119_sor_cnt, .new = gk104_sor_new }, sor 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c .sor = { .cnt = gf119_sor_cnt, .new = gk104_sor_new }, sor 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c .sor = { .cnt = gf119_sor_cnt, .new = gm107_sor_new }, sor 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c .sor = { .cnt = gf119_sor_cnt, .new = gm200_sor_new }, sor 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c .sor = { .cnt = gf119_sor_cnt, .new = gm200_sor_new }, sor 66 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c .sor = { .cnt = gf119_sor_cnt, .new = gm200_sor_new }, sor 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c .sor = { .cnt = nv50_sor_cnt, .new = g84_sor_new }, sor 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c .sor = { .cnt = g94_sor_cnt, .new = gt215_sor_new }, sor 333 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c for (i = 0; i < disp->sor.nr; i++) { sor 422 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c .sor = { .cnt = gv100_sor_cnt, .new = gv100_sor_new }, sor 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c .sor = { .cnt = g94_sor_cnt, .new = mcp77_sor_new }, sor 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c .sor = { .cnt = g94_sor_cnt, .new = mcp89_sor_new }, sor 127 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->sor.nr = func->sor.cnt(&disp->base, &disp->sor.mask); sor 129 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->sor.nr, disp->sor.mask); sor 130 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for_each_set_bit(i, &disp->sor.mask, disp->sor.nr) { sor 131 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ret = func->sor.new(&disp->base, i); sor 453 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c head->asy.or.depth = (disp->sor.lvdsconf & 0x0200) ? 24 : 18; sor 454 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ior->asy.link = (disp->sor.lvdsconf & 0x0100) ? 3 : 1; sor 726 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for (i = 0; i < disp->sor.nr; i++) { sor 767 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c .sor = { .cnt = nv50_sor_cnt, .new = nv50_sor_new }, sor 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h } sor; sor 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h } wndw, head, dac, sor, pior; sor 224 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c disp->sor.lvdsconf = args->v0.script; sor 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark) sor 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 loff = nv50_sor_link(sor); sor 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_dp_activesym(struct nvkm_ior *sor, int head, sor 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 41 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 loff = nv50_sor_link(sor); sor 49 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v) sor 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 soff = nv50_ior_base(sor); sor 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) sor 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 loff = nv50_sor_link(sor); sor 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 shift = sor->func->dp.lanes[ln] * 8; sor 76 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_dp_pattern(struct nvkm_ior *sor, int pattern) sor 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 79 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 loff = nv50_sor_link(sor); sor 84 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_dp_power(struct nvkm_ior *sor, int nr) sor 86 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 87 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 soff = nv50_ior_base(sor); sor 88 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 loff = nv50_sor_link(sor); sor 92 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c mask |= 1 << sor->func->dp.lanes[i]; sor 103 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux) sor 105 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 106 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 soff = nv50_ior_base(sor); sor 107 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 loff = nv50_sor_link(sor); sor 111 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c dpctrl |= ((1 << sor->dp.nr) - 1) << 16; sor 112 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c if (sor->dp.ef) sor 114 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c if (sor->dp.bw > 0x06) sor 123 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_war_needed(struct nvkm_ior *sor) sor 125 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 126 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 soff = nv50_ior_base(sor); sor 127 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c if (sor->asy.proto == TMDS) { sor 169 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_war_3(struct nvkm_ior *sor) sor 171 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 172 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 soff = nv50_ior_base(sor); sor 175 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c if (!g94_sor_war_needed(sor)) sor 207 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_war_update_sppll1(sor->disp); sor 211 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_war_2(struct nvkm_ior *sor) sor 213 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 214 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 soff = nv50_ior_base(sor); sor 216 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c if (!g94_sor_war_needed(sor)) sor 237 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state) sor 239 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 240 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c const u32 coff = sor->id * 8 + (state == &sor->arm) * 4; sor 257 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c nv50_pior_depth(sor, state, ctrl); sor 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c gf119_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark) sor 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c gf119_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v) sor 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 46 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c gf119_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable) sor 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c gf119_sor_dp_vcpi(struct nvkm_ior *sor, int head, sor 63 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) sor 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 74 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c const u32 loff = nv50_sor_link(sor); sor 75 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c const u32 shift = sor->func->dp.lanes[ln] * 8; sor 91 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c gf119_sor_dp_pattern(struct nvkm_ior *sor, int pattern) sor 93 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 94 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c const u32 soff = nv50_ior_base(sor); sor 99 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c gf119_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux) sor 101 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 102 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c const u32 soff = nv50_ior_base(sor); sor 103 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c const u32 loff = nv50_sor_link(sor); sor 107 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c clksor |= sor->dp.bw << 18; sor 108 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c dpctrl |= ((1 << sor->dp.nr) - 1) << 16; sor 109 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c if (sor->dp.mst) sor 111 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c if (sor->dp.ef) sor 120 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c gf119_sor_clock(struct nvkm_ior *sor) sor 122 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 123 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c const u32 soff = nv50_ior_base(sor); sor 124 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c u32 div1 = sor->asy.link == 3; sor 125 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c u32 div2 = sor->asy.link == 3; sor 126 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c if (sor->asy.proto == TMDS) { sor 127 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c const u32 speed = sor->tmds.high_speed ? 0x14 : 0x0a; sor 129 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c if (sor->tmds.high_speed) sor 136 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c gf119_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state) sor 138 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 139 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c const u32 coff = (state == &sor->asy) * 0x20000 + sor->id * 0x20; sor 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c gm107_sor_dp_pattern(struct nvkm_ior *sor, int pattern) sor 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c const u32 soff = nv50_ior_base(sor); sor 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c if (sor->asy.link & 1) sor 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c gm200_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) sor 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c const u32 loff = nv50_sor_link(sor); sor 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c const u32 shift = sor->func->dp.lanes[ln] * 8; sor 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c const u32 sor = ior ? ior->id + 1 : 0; sor 57 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c nvkm_mask(device, 0x612308 + moff, 0x0000001f, link << 4 | sor); sor 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c nvkm_mask(device, 0x612388 + moff, 0x0000001f, link << 4 | sor); sor 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c int lnk[2], sor[2], m, s; sor 76 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c sor[s] = (data & 0x0000000f); sor 77 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c if (!sor[s]) sor 84 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c if (sor[0] != sor[1] || WARN_ON(lnk[0] || !lnk[1])) sor 88 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c return ((sublinks & 1) ? sor[0] : sor[1]) - 1; sor 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c gt215_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable) sor 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c const u32 soff = nv50_ior_base(sor); sor 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c gv100_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark) sor 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c gv100_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v) sor 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c gv100_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable) sor 46 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c gv100_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state) sor 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c const u32 coff = (state == &sor->arm) * 0x8000 + sor->id * 0x20; sor 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c nv50_sor_clock(struct nvkm_ior *sor) sor 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c const int div = sor->asy.link == 3; sor 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c const u32 soff = nv50_ior_base(sor); sor 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c nv50_sor_power(struct nvkm_ior *sor, bool normal, bool pu, sor 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c const u32 soff = nv50_ior_base(sor); sor 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c nv50_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state) sor 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c const u32 coff = sor->id * 8 + (state == &sor->arm) * 4; sor 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head, sor 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 38 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c tu102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux) sor 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c struct nvkm_device *device = sor->disp->engine.subdev.device; sor 41 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c const u32 soff = nv50_ior_base(sor); sor 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c const u32 loff = nv50_sor_link(sor); sor 46 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c clksor |= sor->dp.bw << 18; sor 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c dpctrl |= ((1 << sor->dp.nr) - 1) << 16; sor 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c if (sor->dp.mst) sor 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c if (sor->dp.ef) sor 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c for (i = 0; i < disp->sor.nr; i++) { sor 144 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c .sor = { .cnt = gv100_sor_cnt, .new = tu102_sor_new }, sor 391 drivers/gpu/drm/tegra/sor.c int (*probe)(struct tegra_sor *sor); sor 392 drivers/gpu/drm/tegra/sor.c int (*remove)(struct tegra_sor *sor); sor 474 drivers/gpu/drm/tegra/sor.c static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) sor 476 drivers/gpu/drm/tegra/sor.c u32 value = readl(sor->regs + (offset << 2)); sor 478 drivers/gpu/drm/tegra/sor.c trace_sor_readl(sor->dev, offset, value); sor 483 drivers/gpu/drm/tegra/sor.c static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, sor 486 drivers/gpu/drm/tegra/sor.c trace_sor_writel(sor->dev, offset, value); sor 487 drivers/gpu/drm/tegra/sor.c writel(value, sor->regs + (offset << 2)); sor 490 drivers/gpu/drm/tegra/sor.c static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) sor 494 drivers/gpu/drm/tegra/sor.c clk_disable_unprepare(sor->clk); sor 496 drivers/gpu/drm/tegra/sor.c err = clk_set_parent(sor->clk_out, parent); sor 500 drivers/gpu/drm/tegra/sor.c err = clk_prepare_enable(sor->clk); sor 509 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor; sor 524 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = pad->sor; sor 527 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_CLK_CNTRL); sor 540 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_CLK_CNTRL); sor 548 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = pad->sor; sor 552 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_CLK_CNTRL); sor 574 drivers/gpu/drm/tegra/sor.c static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, sor 581 drivers/gpu/drm/tegra/sor.c pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); sor 585 drivers/gpu/drm/tegra/sor.c pad->sor = sor; sor 595 drivers/gpu/drm/tegra/sor.c clk = devm_clk_register(sor->dev, &pad->hw); sor 600 drivers/gpu/drm/tegra/sor.c static int tegra_sor_dp_train_fast(struct tegra_sor *sor, sor 613 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); sor 619 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); sor 625 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); sor 628 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0, SOR_LVDS); sor 630 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); sor 634 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); sor 636 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); sor 639 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); sor 643 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); sor 646 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); sor 648 drivers/gpu/drm/tegra/sor.c err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B); sor 659 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_TPG); sor 663 drivers/gpu/drm/tegra/sor.c err = drm_dp_aux_train(sor->aux, link, pattern); sor 667 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_DP_SPARE0); sor 671 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_SPARE0); sor 680 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_TPG); sor 684 drivers/gpu/drm/tegra/sor.c err = drm_dp_aux_train(sor->aux, link, pattern); sor 695 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_TPG); sor 699 drivers/gpu/drm/tegra/sor.c err = drm_dp_aux_train(sor->aux, link, pattern); sor 706 drivers/gpu/drm/tegra/sor.c static void tegra_sor_super_update(struct tegra_sor *sor) sor 708 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); sor 709 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); sor 710 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); sor 713 drivers/gpu/drm/tegra/sor.c static void tegra_sor_update(struct tegra_sor *sor) sor 715 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0, SOR_STATE0); sor 716 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 1, SOR_STATE0); sor 717 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0, SOR_STATE0); sor 720 drivers/gpu/drm/tegra/sor.c static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) sor 724 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_PWM_DIV); sor 727 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_PWM_DIV); sor 729 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_PWM_CTL); sor 734 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_PWM_CTL); sor 739 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_PWM_CTL); sor 749 drivers/gpu/drm/tegra/sor.c static int tegra_sor_attach(struct tegra_sor *sor) sor 754 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_SUPER_STATE1); sor 757 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_SUPER_STATE1); sor 758 drivers/gpu/drm/tegra/sor.c tegra_sor_super_update(sor); sor 761 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_SUPER_STATE1); sor 763 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_SUPER_STATE1); sor 764 drivers/gpu/drm/tegra/sor.c tegra_sor_super_update(sor); sor 769 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_TEST); sor 779 drivers/gpu/drm/tegra/sor.c static int tegra_sor_wakeup(struct tegra_sor *sor) sor 787 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_TEST); sor 799 drivers/gpu/drm/tegra/sor.c static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) sor 803 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_PWR); sor 805 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_PWR); sor 810 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_PWR); sor 835 drivers/gpu/drm/tegra/sor.c static int tegra_sor_compute_params(struct tegra_sor *sor, sor 903 drivers/gpu/drm/tegra/sor.c static int tegra_sor_compute_config(struct tegra_sor *sor, sor 932 drivers/gpu/drm/tegra/sor.c if (tegra_sor_compute_params(sor, ¶ms, i)) sor 951 drivers/gpu/drm/tegra/sor.c dev_dbg(sor->dev, sor 966 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, sor 971 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "watermark too high, forcing to %u\n", sor 989 drivers/gpu/drm/tegra/sor.c dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, sor 995 drivers/gpu/drm/tegra/sor.c static void tegra_sor_apply_config(struct tegra_sor *sor, sor 1000 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); sor 1003 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); sor 1005 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_DP_CONFIG0); sor 1022 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_CONFIG0); sor 1024 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); sor 1027 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); sor 1029 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); sor 1032 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); sor 1035 drivers/gpu/drm/tegra/sor.c static void tegra_sor_mode_set(struct tegra_sor *sor, sor 1039 drivers/gpu/drm/tegra/sor.c struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); sor 1043 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_STATE1); sor 1089 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_STATE1); sor 1097 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); sor 1104 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); sor 1111 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); sor 1118 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); sor 1121 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); sor 1124 drivers/gpu/drm/tegra/sor.c static int tegra_sor_detach(struct tegra_sor *sor) sor 1129 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_SUPER_STATE1); sor 1131 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_SUPER_STATE1); sor 1132 drivers/gpu/drm/tegra/sor.c tegra_sor_super_update(sor); sor 1137 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_PWR); sor 1146 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_SUPER_STATE1); sor 1148 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_SUPER_STATE1); sor 1149 drivers/gpu/drm/tegra/sor.c tegra_sor_super_update(sor); sor 1152 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_SUPER_STATE1); sor 1154 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_SUPER_STATE1); sor 1155 drivers/gpu/drm/tegra/sor.c tegra_sor_super_update(sor); sor 1160 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_TEST); sor 1173 drivers/gpu/drm/tegra/sor.c static int tegra_sor_power_down(struct tegra_sor *sor) sor 1178 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_PWR); sor 1181 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_PWR); sor 1186 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_PWR); sor 1197 drivers/gpu/drm/tegra/sor.c err = tegra_sor_set_parent_clock(sor, sor->clk_safe); sor 1199 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); sor 1203 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); sor 1206 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); sor 1211 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); sor 1216 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); sor 1226 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); sor 1228 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); sor 1232 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll0); sor 1234 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll0); sor 1236 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); sor 1239 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); sor 1246 drivers/gpu/drm/tegra/sor.c static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) sor 1253 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_CRCA); sor 1266 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = node->info_ent->data; sor 1267 drivers/gpu/drm/tegra/sor.c struct drm_crtc *crtc = sor->output.encoder.crtc; sor 1279 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_STATE1); sor 1281 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_STATE1); sor 1283 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_CRC_CNTRL); sor 1285 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_CRC_CNTRL); sor 1287 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_TEST); sor 1289 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_TEST); sor 1291 drivers/gpu/drm/tegra/sor.c err = tegra_sor_crc_wait(sor, 100); sor 1295 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); sor 1296 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_CRCB); sor 1428 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = node->info_ent->data; sor 1429 drivers/gpu/drm/tegra/sor.c struct drm_crtc *crtc = sor->output.encoder.crtc; sor 1445 drivers/gpu/drm/tegra/sor.c offset, tegra_sor_readl(sor, offset)); sor 1464 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = to_sor(output); sor 1467 drivers/gpu/drm/tegra/sor.c sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), sor 1469 drivers/gpu/drm/tegra/sor.c if (!sor->debugfs_files) sor 1473 drivers/gpu/drm/tegra/sor.c sor->debugfs_files[i].data = sor; sor 1475 drivers/gpu/drm/tegra/sor.c err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor); sor 1482 drivers/gpu/drm/tegra/sor.c kfree(sor->debugfs_files); sor 1483 drivers/gpu/drm/tegra/sor.c sor->debugfs_files = NULL; sor 1492 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = to_sor(output); sor 1494 drivers/gpu/drm/tegra/sor.c drm_debugfs_remove_files(sor->debugfs_files, count, sor 1496 drivers/gpu/drm/tegra/sor.c kfree(sor->debugfs_files); sor 1497 drivers/gpu/drm/tegra/sor.c sor->debugfs_files = NULL; sor 1520 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = to_sor(output); sor 1522 drivers/gpu/drm/tegra/sor.c if (sor->aux) sor 1523 drivers/gpu/drm/tegra/sor.c return drm_dp_aux_detect(sor->aux); sor 1557 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = to_sor(output); sor 1560 drivers/gpu/drm/tegra/sor.c if (sor->aux) sor 1561 drivers/gpu/drm/tegra/sor.c drm_dp_aux_enable(sor->aux); sor 1565 drivers/gpu/drm/tegra/sor.c if (sor->aux) sor 1566 drivers/gpu/drm/tegra/sor.c drm_dp_aux_disable(sor->aux); sor 1591 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = to_sor(output); sor 1598 drivers/gpu/drm/tegra/sor.c err = tegra_sor_detach(sor); sor 1600 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to detach SOR: %d\n", err); sor 1602 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0, SOR_STATE1); sor 1603 drivers/gpu/drm/tegra/sor.c tegra_sor_update(sor); sor 1617 drivers/gpu/drm/tegra/sor.c err = tegra_sor_power_down(sor); sor 1619 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to power down SOR: %d\n", err); sor 1621 drivers/gpu/drm/tegra/sor.c if (sor->aux) { sor 1622 drivers/gpu/drm/tegra/sor.c err = drm_dp_aux_disable(sor->aux); sor 1624 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to disable DP: %d\n", err); sor 1627 drivers/gpu/drm/tegra/sor.c err = tegra_io_pad_power_disable(sor->pad); sor 1629 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); sor 1634 drivers/gpu/drm/tegra/sor.c pm_runtime_put(sor->dev); sor 1684 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = to_sor(output); sor 1695 drivers/gpu/drm/tegra/sor.c pm_runtime_get_sync(sor->dev); sor 1700 drivers/gpu/drm/tegra/sor.c err = drm_dp_aux_enable(sor->aux); sor 1702 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to enable DP: %d\n", err); sor 1704 drivers/gpu/drm/tegra/sor.c err = drm_dp_link_probe(sor->aux, &link); sor 1706 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to probe eDP link: %d\n", err); sor 1711 drivers/gpu/drm/tegra/sor.c err = tegra_sor_set_parent_clock(sor, sor->clk_safe); sor 1713 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); sor 1718 drivers/gpu/drm/tegra/sor.c err = tegra_sor_compute_config(sor, mode, &config, &link); sor 1720 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to compute configuration: %d\n", err); sor 1722 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_CLK_CNTRL); sor 1725 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_CLK_CNTRL); sor 1727 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); sor 1729 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); sor 1732 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll3); sor 1734 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll3); sor 1738 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll0); sor 1740 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); sor 1744 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); sor 1747 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll1); sor 1750 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); sor 1757 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); sor 1760 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); sor 1767 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_CLK_CNTRL); sor 1770 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_CLK_CNTRL); sor 1773 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); sor 1776 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); sor 1778 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll0); sor 1780 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll0); sor 1782 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); sor 1784 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); sor 1787 drivers/gpu/drm/tegra/sor.c err = tegra_io_pad_power_enable(sor->pad); sor 1789 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); sor 1794 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); sor 1796 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); sor 1801 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll0); sor 1804 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll0); sor 1806 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); sor 1808 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); sor 1813 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); sor 1815 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); sor 1819 drivers/gpu/drm/tegra/sor.c value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | sor 1822 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); sor 1823 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_XBAR_CTRL); sor 1826 drivers/gpu/drm/tegra/sor.c err = tegra_sor_set_parent_clock(sor, sor->clk_dp); sor 1828 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to set parent clock: %d\n", err); sor 1831 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); sor 1848 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); sor 1850 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); sor 1853 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); sor 1858 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); sor 1861 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); sor 1869 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_CLK_CNTRL); sor 1872 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_CLK_CNTRL); sor 1874 drivers/gpu/drm/tegra/sor.c tegra_sor_apply_config(sor, &config); sor 1877 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); sor 1880 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); sor 1889 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_TPG); sor 1892 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); sor 1894 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); sor 1896 drivers/gpu/drm/tegra/sor.c err = drm_dp_link_probe(sor->aux, &link); sor 1898 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to probe eDP link: %d\n", err); sor 1900 drivers/gpu/drm/tegra/sor.c err = drm_dp_link_power_up(sor->aux, &link); sor 1902 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to power up eDP link: %d\n", err); sor 1904 drivers/gpu/drm/tegra/sor.c err = drm_dp_link_configure(sor->aux, &link); sor 1906 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to configure eDP link: %d\n", err); sor 1911 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_CLK_CNTRL); sor 1914 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_CLK_CNTRL); sor 1916 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); sor 1923 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); sor 1934 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_TPG); sor 1936 drivers/gpu/drm/tegra/sor.c err = tegra_sor_dp_train_fast(sor, &link); sor 1938 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "DP fast link training failed: %d\n", err); sor 1940 drivers/gpu/drm/tegra/sor.c dev_dbg(sor->dev, "fast link training succeeded\n"); sor 1942 drivers/gpu/drm/tegra/sor.c err = tegra_sor_power_up(sor, 250); sor 1944 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to power up SOR: %d\n", err); sor 1949 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_CSTM); sor 1952 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_STATE1); sor 1955 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_STATE1); sor 1957 drivers/gpu/drm/tegra/sor.c tegra_sor_mode_set(sor, mode, state); sor 1960 drivers/gpu/drm/tegra/sor.c err = tegra_sor_setup_pwm(sor, 250); sor 1962 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to setup PWM: %d\n", err); sor 1964 drivers/gpu/drm/tegra/sor.c tegra_sor_update(sor); sor 1972 drivers/gpu/drm/tegra/sor.c err = tegra_sor_attach(sor); sor 1974 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to attach SOR: %d\n", err); sor 1976 drivers/gpu/drm/tegra/sor.c err = tegra_sor_wakeup(sor); sor 1978 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to enable DC: %d\n", err); sor 1993 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = to_sor(output); sor 2011 drivers/gpu/drm/tegra/sor.c err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, sor 2050 drivers/gpu/drm/tegra/sor.c static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, sor 2072 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "unsupported infoframe type: %02x\n", sor 2080 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, offset); sor 2092 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, offset++); sor 2097 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, offset++); sor 2102 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, sor 2111 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); sor 2115 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); sor 2118 drivers/gpu/drm/tegra/sor.c &sor->output.connector, mode); sor 2120 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); sor 2126 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); sor 2130 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_write_infopack(sor, buffer, err); sor 2133 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); sor 2136 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); sor 2141 drivers/gpu/drm/tegra/sor.c static void tegra_sor_write_eld(struct tegra_sor *sor) sor 2143 drivers/gpu/drm/tegra/sor.c size_t length = drm_eld_size(sor->output.connector.eld), i; sor 2146 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], sor 2156 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR); sor 2159 drivers/gpu/drm/tegra/sor.c static void tegra_sor_audio_prepare(struct tegra_sor *sor) sor 2163 drivers/gpu/drm/tegra/sor.c tegra_sor_write_eld(sor); sor 2166 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); sor 2169 drivers/gpu/drm/tegra/sor.c static void tegra_sor_audio_unprepare(struct tegra_sor *sor) sor 2171 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE); sor 2174 drivers/gpu/drm/tegra/sor.c static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) sor 2183 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); sor 2187 drivers/gpu/drm/tegra/sor.c frame.channels = sor->format.channels; sor 2191 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); sor 2195 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_write_infopack(sor, buffer, err); sor 2197 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); sor 2200 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); sor 2205 drivers/gpu/drm/tegra/sor.c static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) sor 2209 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); sor 2216 drivers/gpu/drm/tegra/sor.c if (sor->format.channels != 2) sor 2223 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); sor 2226 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); sor 2228 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); sor 2233 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_HDMI_SPARE); sor 2237 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); sor 2241 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); sor 2245 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); sor 2247 drivers/gpu/drm/tegra/sor.c value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); sor 2248 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); sor 2249 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320); sor 2251 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441); sor 2252 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441); sor 2254 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882); sor 2255 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882); sor 2257 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764); sor 2258 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764); sor 2260 drivers/gpu/drm/tegra/sor.c value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); sor 2261 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); sor 2262 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480); sor 2264 drivers/gpu/drm/tegra/sor.c value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); sor 2265 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); sor 2266 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960); sor 2268 drivers/gpu/drm/tegra/sor.c value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); sor 2269 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); sor 2270 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920); sor 2272 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); sor 2274 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); sor 2276 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_enable_audio_infoframe(sor); sor 2279 drivers/gpu/drm/tegra/sor.c static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) sor 2283 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); sor 2285 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); sor 2288 drivers/gpu/drm/tegra/sor.c static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor) sor 2290 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_disable_audio_infoframe(sor); sor 2294 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) sor 2298 drivers/gpu/drm/tegra/sor.c for (i = 0; i < sor->num_settings; i++) sor 2299 drivers/gpu/drm/tegra/sor.c if (frequency <= sor->settings[i].frequency) sor 2300 drivers/gpu/drm/tegra/sor.c return &sor->settings[i]; sor 2305 drivers/gpu/drm/tegra/sor.c static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) sor 2309 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); sor 2312 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); sor 2315 drivers/gpu/drm/tegra/sor.c static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) sor 2317 drivers/gpu/drm/tegra/sor.c struct i2c_adapter *ddc = sor->output.ddc; sor 2322 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_disable_scrambling(sor); sor 2325 drivers/gpu/drm/tegra/sor.c static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) sor 2327 drivers/gpu/drm/tegra/sor.c if (sor->scdc_enabled) { sor 2328 drivers/gpu/drm/tegra/sor.c cancel_delayed_work_sync(&sor->scdc); sor 2329 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_scdc_disable(sor); sor 2333 drivers/gpu/drm/tegra/sor.c static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) sor 2337 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); sor 2340 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); sor 2343 drivers/gpu/drm/tegra/sor.c static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) sor 2345 drivers/gpu/drm/tegra/sor.c struct i2c_adapter *ddc = sor->output.ddc; sor 2350 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_enable_scrambling(sor); sor 2355 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); sor 2356 drivers/gpu/drm/tegra/sor.c struct i2c_adapter *ddc = sor->output.ddc; sor 2360 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_scdc_enable(sor); sor 2363 drivers/gpu/drm/tegra/sor.c schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); sor 2366 drivers/gpu/drm/tegra/sor.c static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) sor 2368 drivers/gpu/drm/tegra/sor.c struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; sor 2371 drivers/gpu/drm/tegra/sor.c mode = &sor->output.encoder.crtc->state->adjusted_mode; sor 2374 drivers/gpu/drm/tegra/sor.c schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); sor 2375 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_scdc_enable(sor); sor 2376 drivers/gpu/drm/tegra/sor.c sor->scdc_enabled = true; sor 2384 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = to_sor(output); sor 2388 drivers/gpu/drm/tegra/sor.c tegra_sor_audio_unprepare(sor); sor 2389 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_scdc_stop(sor); sor 2391 drivers/gpu/drm/tegra/sor.c err = tegra_sor_detach(sor); sor 2393 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to detach SOR: %d\n", err); sor 2395 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0, SOR_STATE1); sor 2396 drivers/gpu/drm/tegra/sor.c tegra_sor_update(sor); sor 2401 drivers/gpu/drm/tegra/sor.c if (!sor->soc->has_nvdisplay) sor 2404 drivers/gpu/drm/tegra/sor.c value &= ~SOR_ENABLE(sor->index); sor 2410 drivers/gpu/drm/tegra/sor.c err = tegra_sor_power_down(sor); sor 2412 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to power down SOR: %d\n", err); sor 2414 drivers/gpu/drm/tegra/sor.c err = tegra_io_pad_power_disable(sor->pad); sor 2416 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); sor 2418 drivers/gpu/drm/tegra/sor.c pm_runtime_put(sor->dev); sor 2427 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = to_sor(output); sor 2439 drivers/gpu/drm/tegra/sor.c pm_runtime_get_sync(sor->dev); sor 2442 drivers/gpu/drm/tegra/sor.c err = tegra_sor_set_parent_clock(sor, sor->clk_safe); sor 2444 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); sor 2448 drivers/gpu/drm/tegra/sor.c div = clk_get_rate(sor->clk) / 1000000 * 4; sor 2450 drivers/gpu/drm/tegra/sor.c err = tegra_io_pad_power_enable(sor->pad); sor 2452 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); sor 2456 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); sor 2458 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); sor 2462 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll3); sor 2464 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll3); sor 2466 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll0); sor 2469 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll0); sor 2471 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); sor 2473 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); sor 2477 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); sor 2480 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); sor 2484 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); sor 2487 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); sor 2490 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); sor 2499 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); sor 2502 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); sor 2509 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_CLK_CNTRL); sor 2522 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_CLK_CNTRL); sor 2527 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); sor 2530 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); sor 2532 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_DP_SPARE0); sor 2537 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_SPARE0); sor 2541 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_SEQ_CTL); sor 2545 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); sor 2546 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); sor 2548 drivers/gpu/drm/tegra/sor.c if (!sor->soc->has_nvdisplay) { sor 2551 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_REFCLK); sor 2556 drivers/gpu/drm/tegra/sor.c value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | sor 2559 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); sor 2560 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_XBAR_CTRL); sor 2563 drivers/gpu/drm/tegra/sor.c err = clk_set_parent(sor->clk, sor->clk_parent); sor 2565 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to set parent clock: %d\n", err); sor 2569 drivers/gpu/drm/tegra/sor.c err = tegra_sor_set_parent_clock(sor, sor->clk_pad); sor 2571 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to set pad clock: %d\n", err); sor 2576 drivers/gpu/drm/tegra/sor.c rate = clk_get_rate(sor->clk_parent); sor 2583 drivers/gpu/drm/tegra/sor.c clk_set_rate(sor->clk, rate); sor 2585 drivers/gpu/drm/tegra/sor.c if (!sor->soc->has_nvdisplay) { sor 2592 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); sor 2599 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_HDMI_CTRL); sor 2620 drivers/gpu/drm/tegra/sor.c err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); sor 2622 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); sor 2625 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_disable_audio_infoframe(sor); sor 2628 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_STATE1); sor 2631 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_STATE1); sor 2634 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); sor 2636 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); sor 2639 drivers/gpu/drm/tegra/sor.c settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); sor 2641 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "no settings for pixel clock %d Hz\n", sor 2646 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll0); sor 2653 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll0); sor 2656 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll1); sor 2662 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll1); sor 2664 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll3); sor 2673 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll3); sor 2679 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); sor 2685 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); sor 2687 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); sor 2691 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); sor 2693 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); sor 2696 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); sor 2699 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); sor 2701 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); sor 2739 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_STATE1); sor 2742 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_STATE1); sor 2744 drivers/gpu/drm/tegra/sor.c err = tegra_sor_power_up(sor, 250); sor 2746 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to power up SOR: %d\n", err); sor 2749 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); sor 2752 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); sor 2755 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); sor 2758 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); sor 2760 drivers/gpu/drm/tegra/sor.c tegra_sor_mode_set(sor, mode, state); sor 2762 drivers/gpu/drm/tegra/sor.c tegra_sor_update(sor); sor 2765 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_DP_SPARE0); sor 2767 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_DP_SPARE0); sor 2769 drivers/gpu/drm/tegra/sor.c err = tegra_sor_attach(sor); sor 2771 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to attach SOR: %d\n", err); sor 2776 drivers/gpu/drm/tegra/sor.c if (!sor->soc->has_nvdisplay) sor 2779 drivers/gpu/drm/tegra/sor.c value |= SOR_ENABLE(sor->index); sor 2784 drivers/gpu/drm/tegra/sor.c value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); sor 2787 drivers/gpu/drm/tegra/sor.c tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); sor 2792 drivers/gpu/drm/tegra/sor.c err = tegra_sor_wakeup(sor); sor 2794 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); sor 2796 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_scdc_start(sor); sor 2797 drivers/gpu/drm/tegra/sor.c tegra_sor_audio_prepare(sor); sor 2810 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = host1x_client_to_sor(client); sor 2816 drivers/gpu/drm/tegra/sor.c if (!sor->aux) { sor 2817 drivers/gpu/drm/tegra/sor.c if (sor->soc->supports_hdmi) { sor 2821 drivers/gpu/drm/tegra/sor.c } else if (sor->soc->supports_lvds) { sor 2826 drivers/gpu/drm/tegra/sor.c if (sor->soc->supports_edp) { sor 2830 drivers/gpu/drm/tegra/sor.c } else if (sor->soc->supports_dp) { sor 2836 drivers/gpu/drm/tegra/sor.c sor->output.dev = sor->dev; sor 2838 drivers/gpu/drm/tegra/sor.c drm_connector_init(drm, &sor->output.connector, sor 2841 drivers/gpu/drm/tegra/sor.c drm_connector_helper_add(&sor->output.connector, sor 2843 drivers/gpu/drm/tegra/sor.c sor->output.connector.dpms = DRM_MODE_DPMS_OFF; sor 2845 drivers/gpu/drm/tegra/sor.c drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, sor 2847 drivers/gpu/drm/tegra/sor.c drm_encoder_helper_add(&sor->output.encoder, helpers); sor 2849 drivers/gpu/drm/tegra/sor.c drm_connector_attach_encoder(&sor->output.connector, sor 2850 drivers/gpu/drm/tegra/sor.c &sor->output.encoder); sor 2851 drivers/gpu/drm/tegra/sor.c drm_connector_register(&sor->output.connector); sor 2853 drivers/gpu/drm/tegra/sor.c err = tegra_output_init(drm, &sor->output); sor 2859 drivers/gpu/drm/tegra/sor.c tegra_output_find_possible_crtcs(&sor->output, drm); sor 2861 drivers/gpu/drm/tegra/sor.c if (sor->aux) { sor 2862 drivers/gpu/drm/tegra/sor.c err = drm_dp_aux_attach(sor->aux, &sor->output); sor 2864 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to attach DP: %d\n", err); sor 2873 drivers/gpu/drm/tegra/sor.c if (sor->rst) { sor 2874 drivers/gpu/drm/tegra/sor.c err = reset_control_acquire(sor->rst); sor 2876 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to acquire SOR reset: %d\n", sor 2881 drivers/gpu/drm/tegra/sor.c err = reset_control_assert(sor->rst); sor 2883 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to assert SOR reset: %d\n", sor 2889 drivers/gpu/drm/tegra/sor.c err = clk_prepare_enable(sor->clk); sor 2891 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to enable clock: %d\n", err); sor 2897 drivers/gpu/drm/tegra/sor.c if (sor->rst) { sor 2898 drivers/gpu/drm/tegra/sor.c err = reset_control_deassert(sor->rst); sor 2900 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to deassert SOR reset: %d\n", sor 2905 drivers/gpu/drm/tegra/sor.c reset_control_release(sor->rst); sor 2908 drivers/gpu/drm/tegra/sor.c err = clk_prepare_enable(sor->clk_safe); sor 2912 drivers/gpu/drm/tegra/sor.c err = clk_prepare_enable(sor->clk_dp); sor 2922 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_INT_ENABLE); sor 2923 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_INT_MASK); sor 2930 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = host1x_client_to_sor(client); sor 2933 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0, SOR_INT_MASK); sor 2934 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, 0, SOR_INT_ENABLE); sor 2936 drivers/gpu/drm/tegra/sor.c tegra_output_exit(&sor->output); sor 2938 drivers/gpu/drm/tegra/sor.c if (sor->aux) { sor 2939 drivers/gpu/drm/tegra/sor.c err = drm_dp_aux_detach(sor->aux); sor 2941 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to detach DP: %d\n", err); sor 2946 drivers/gpu/drm/tegra/sor.c clk_disable_unprepare(sor->clk_safe); sor 2947 drivers/gpu/drm/tegra/sor.c clk_disable_unprepare(sor->clk_dp); sor 2948 drivers/gpu/drm/tegra/sor.c clk_disable_unprepare(sor->clk); sor 2962 drivers/gpu/drm/tegra/sor.c static int tegra_sor_hdmi_probe(struct tegra_sor *sor) sor 2966 drivers/gpu/drm/tegra/sor.c sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); sor 2967 drivers/gpu/drm/tegra/sor.c if (IS_ERR(sor->avdd_io_supply)) { sor 2968 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", sor 2969 drivers/gpu/drm/tegra/sor.c PTR_ERR(sor->avdd_io_supply)); sor 2970 drivers/gpu/drm/tegra/sor.c return PTR_ERR(sor->avdd_io_supply); sor 2973 drivers/gpu/drm/tegra/sor.c err = regulator_enable(sor->avdd_io_supply); sor 2975 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", sor 2980 drivers/gpu/drm/tegra/sor.c sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); sor 2981 drivers/gpu/drm/tegra/sor.c if (IS_ERR(sor->vdd_pll_supply)) { sor 2982 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", sor 2983 drivers/gpu/drm/tegra/sor.c PTR_ERR(sor->vdd_pll_supply)); sor 2984 drivers/gpu/drm/tegra/sor.c return PTR_ERR(sor->vdd_pll_supply); sor 2987 drivers/gpu/drm/tegra/sor.c err = regulator_enable(sor->vdd_pll_supply); sor 2989 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", sor 2994 drivers/gpu/drm/tegra/sor.c sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); sor 2995 drivers/gpu/drm/tegra/sor.c if (IS_ERR(sor->hdmi_supply)) { sor 2996 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "cannot get HDMI supply: %ld\n", sor 2997 drivers/gpu/drm/tegra/sor.c PTR_ERR(sor->hdmi_supply)); sor 2998 drivers/gpu/drm/tegra/sor.c return PTR_ERR(sor->hdmi_supply); sor 3001 drivers/gpu/drm/tegra/sor.c err = regulator_enable(sor->hdmi_supply); sor 3003 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); sor 3007 drivers/gpu/drm/tegra/sor.c INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); sor 3012 drivers/gpu/drm/tegra/sor.c static int tegra_sor_hdmi_remove(struct tegra_sor *sor) sor 3014 drivers/gpu/drm/tegra/sor.c regulator_disable(sor->hdmi_supply); sor 3015 drivers/gpu/drm/tegra/sor.c regulator_disable(sor->vdd_pll_supply); sor 3016 drivers/gpu/drm/tegra/sor.c regulator_disable(sor->avdd_io_supply); sor 3183 drivers/gpu/drm/tegra/sor.c static int tegra_sor_parse_dt(struct tegra_sor *sor) sor 3185 drivers/gpu/drm/tegra/sor.c struct device_node *np = sor->dev->of_node; sor 3191 drivers/gpu/drm/tegra/sor.c if (sor->soc->has_nvdisplay) { sor 3196 drivers/gpu/drm/tegra/sor.c sor->index = value; sor 3202 drivers/gpu/drm/tegra/sor.c sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; sor 3204 drivers/gpu/drm/tegra/sor.c if (sor->soc->supports_edp) sor 3205 drivers/gpu/drm/tegra/sor.c sor->index = 0; sor 3207 drivers/gpu/drm/tegra/sor.c sor->index = 1; sor 3214 drivers/gpu/drm/tegra/sor.c sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; sor 3218 drivers/gpu/drm/tegra/sor.c sor->xbar_cfg[i] = xbar_cfg[i]; sor 3226 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = data; sor 3229 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_INT_STATUS); sor 3230 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, SOR_INT_STATUS); sor 3233 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); sor 3240 drivers/gpu/drm/tegra/sor.c tegra_hda_parse_format(format, &sor->format); sor 3242 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_audio_enable(sor); sor 3244 drivers/gpu/drm/tegra/sor.c tegra_sor_hdmi_audio_disable(sor); sor 3254 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor; sor 3258 drivers/gpu/drm/tegra/sor.c sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); sor 3259 drivers/gpu/drm/tegra/sor.c if (!sor) sor 3262 drivers/gpu/drm/tegra/sor.c sor->soc = of_device_get_match_data(&pdev->dev); sor 3263 drivers/gpu/drm/tegra/sor.c sor->output.dev = sor->dev = &pdev->dev; sor 3265 drivers/gpu/drm/tegra/sor.c sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, sor 3266 drivers/gpu/drm/tegra/sor.c sor->soc->num_settings * sor 3267 drivers/gpu/drm/tegra/sor.c sizeof(*sor->settings), sor 3269 drivers/gpu/drm/tegra/sor.c if (!sor->settings) sor 3272 drivers/gpu/drm/tegra/sor.c sor->num_settings = sor->soc->num_settings; sor 3276 drivers/gpu/drm/tegra/sor.c sor->aux = drm_dp_aux_find_by_of_node(np); sor 3279 drivers/gpu/drm/tegra/sor.c if (!sor->aux) sor 3283 drivers/gpu/drm/tegra/sor.c if (!sor->aux) { sor 3284 drivers/gpu/drm/tegra/sor.c if (sor->soc->supports_hdmi) { sor 3285 drivers/gpu/drm/tegra/sor.c sor->ops = &tegra_sor_hdmi_ops; sor 3286 drivers/gpu/drm/tegra/sor.c sor->pad = TEGRA_IO_PAD_HDMI; sor 3287 drivers/gpu/drm/tegra/sor.c } else if (sor->soc->supports_lvds) { sor 3295 drivers/gpu/drm/tegra/sor.c if (sor->soc->supports_edp) { sor 3296 drivers/gpu/drm/tegra/sor.c sor->ops = &tegra_sor_edp_ops; sor 3297 drivers/gpu/drm/tegra/sor.c sor->pad = TEGRA_IO_PAD_LVDS; sor 3298 drivers/gpu/drm/tegra/sor.c } else if (sor->soc->supports_dp) { sor 3307 drivers/gpu/drm/tegra/sor.c err = tegra_sor_parse_dt(sor); sor 3311 drivers/gpu/drm/tegra/sor.c err = tegra_output_probe(&sor->output); sor 3317 drivers/gpu/drm/tegra/sor.c if (sor->ops && sor->ops->probe) { sor 3318 drivers/gpu/drm/tegra/sor.c err = sor->ops->probe(sor); sor 3321 drivers/gpu/drm/tegra/sor.c sor->ops->name, err); sor 3327 drivers/gpu/drm/tegra/sor.c sor->regs = devm_ioremap_resource(&pdev->dev, regs); sor 3328 drivers/gpu/drm/tegra/sor.c if (IS_ERR(sor->regs)) { sor 3329 drivers/gpu/drm/tegra/sor.c err = PTR_ERR(sor->regs); sor 3339 drivers/gpu/drm/tegra/sor.c sor->irq = err; sor 3341 drivers/gpu/drm/tegra/sor.c err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, sor 3342 drivers/gpu/drm/tegra/sor.c dev_name(sor->dev), sor); sor 3348 drivers/gpu/drm/tegra/sor.c sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); sor 3349 drivers/gpu/drm/tegra/sor.c if (IS_ERR(sor->rst)) { sor 3350 drivers/gpu/drm/tegra/sor.c err = PTR_ERR(sor->rst); sor 3364 drivers/gpu/drm/tegra/sor.c sor->rst = NULL; sor 3367 drivers/gpu/drm/tegra/sor.c sor->clk = devm_clk_get(&pdev->dev, NULL); sor 3368 drivers/gpu/drm/tegra/sor.c if (IS_ERR(sor->clk)) { sor 3369 drivers/gpu/drm/tegra/sor.c err = PTR_ERR(sor->clk); sor 3374 drivers/gpu/drm/tegra/sor.c if (sor->soc->supports_hdmi || sor->soc->supports_dp) { sor 3388 drivers/gpu/drm/tegra/sor.c sor->clk_out = devm_clk_get(&pdev->dev, name); sor 3389 drivers/gpu/drm/tegra/sor.c if (IS_ERR(sor->clk_out)) { sor 3390 drivers/gpu/drm/tegra/sor.c err = PTR_ERR(sor->clk_out); sor 3391 drivers/gpu/drm/tegra/sor.c dev_err(sor->dev, "failed to get %s clock: %d\n", sor 3397 drivers/gpu/drm/tegra/sor.c sor->clk_out = sor->clk; sor 3400 drivers/gpu/drm/tegra/sor.c sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); sor 3401 drivers/gpu/drm/tegra/sor.c if (IS_ERR(sor->clk_parent)) { sor 3402 drivers/gpu/drm/tegra/sor.c err = PTR_ERR(sor->clk_parent); sor 3407 drivers/gpu/drm/tegra/sor.c sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); sor 3408 drivers/gpu/drm/tegra/sor.c if (IS_ERR(sor->clk_safe)) { sor 3409 drivers/gpu/drm/tegra/sor.c err = PTR_ERR(sor->clk_safe); sor 3414 drivers/gpu/drm/tegra/sor.c sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); sor 3415 drivers/gpu/drm/tegra/sor.c if (IS_ERR(sor->clk_dp)) { sor 3416 drivers/gpu/drm/tegra/sor.c err = PTR_ERR(sor->clk_dp); sor 3425 drivers/gpu/drm/tegra/sor.c sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); sor 3426 drivers/gpu/drm/tegra/sor.c if (IS_ERR(sor->clk_pad)) { sor 3427 drivers/gpu/drm/tegra/sor.c if (sor->clk_pad != ERR_PTR(-ENOENT)) { sor 3428 drivers/gpu/drm/tegra/sor.c err = PTR_ERR(sor->clk_pad); sor 3437 drivers/gpu/drm/tegra/sor.c sor->clk_pad = NULL; sor 3445 drivers/gpu/drm/tegra/sor.c err = clk_set_parent(sor->clk_out, sor->clk_safe); sor 3451 drivers/gpu/drm/tegra/sor.c platform_set_drvdata(pdev, sor); sor 3458 drivers/gpu/drm/tegra/sor.c if (!sor->clk_pad) { sor 3466 drivers/gpu/drm/tegra/sor.c sor->clk_pad = tegra_clk_sor_pad_register(sor, sor 3471 drivers/gpu/drm/tegra/sor.c if (IS_ERR(sor->clk_pad)) { sor 3472 drivers/gpu/drm/tegra/sor.c err = PTR_ERR(sor->clk_pad); sor 3478 drivers/gpu/drm/tegra/sor.c INIT_LIST_HEAD(&sor->client.list); sor 3479 drivers/gpu/drm/tegra/sor.c sor->client.ops = &sor_client_ops; sor 3480 drivers/gpu/drm/tegra/sor.c sor->client.dev = &pdev->dev; sor 3482 drivers/gpu/drm/tegra/sor.c err = host1x_client_register(&sor->client); sor 3492 drivers/gpu/drm/tegra/sor.c if (sor->ops && sor->ops->remove) sor 3493 drivers/gpu/drm/tegra/sor.c sor->ops->remove(sor); sor 3495 drivers/gpu/drm/tegra/sor.c tegra_output_remove(&sor->output); sor 3501 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = platform_get_drvdata(pdev); sor 3506 drivers/gpu/drm/tegra/sor.c err = host1x_client_unregister(&sor->client); sor 3513 drivers/gpu/drm/tegra/sor.c if (sor->ops && sor->ops->remove) { sor 3514 drivers/gpu/drm/tegra/sor.c err = sor->ops->remove(sor); sor 3519 drivers/gpu/drm/tegra/sor.c tegra_output_remove(&sor->output); sor 3527 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = dev_get_drvdata(dev); sor 3530 drivers/gpu/drm/tegra/sor.c if (sor->rst) { sor 3531 drivers/gpu/drm/tegra/sor.c err = reset_control_assert(sor->rst); sor 3537 drivers/gpu/drm/tegra/sor.c reset_control_release(sor->rst); sor 3542 drivers/gpu/drm/tegra/sor.c clk_disable_unprepare(sor->clk); sor 3549 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = dev_get_drvdata(dev); sor 3552 drivers/gpu/drm/tegra/sor.c err = clk_prepare_enable(sor->clk); sor 3560 drivers/gpu/drm/tegra/sor.c if (sor->rst) { sor 3561 drivers/gpu/drm/tegra/sor.c err = reset_control_acquire(sor->rst); sor 3564 drivers/gpu/drm/tegra/sor.c clk_disable_unprepare(sor->clk); sor 3568 drivers/gpu/drm/tegra/sor.c err = reset_control_deassert(sor->rst); sor 3571 drivers/gpu/drm/tegra/sor.c reset_control_release(sor->rst); sor 3572 drivers/gpu/drm/tegra/sor.c clk_disable_unprepare(sor->clk);