soft_regs_start 600 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pi->soft_regs_start = tmp; soft_regs_start 1408 drivers/gpu/drm/amd/amdgpu/kv_dpm.c return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset, soft_regs_start 1417 drivers/gpu/drm/amd/amdgpu/kv_dpm.c return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset, soft_regs_start 149 drivers/gpu/drm/amd/amdgpu/kv_dpm.h u32 soft_regs_start; soft_regs_start 3649 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->soft_regs_start + reg_offset, value, soft_regs_start 3660 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->soft_regs_start + reg_offset, soft_regs_start 3960 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->soft_regs_start = tmp; soft_regs_start 592 drivers/gpu/drm/amd/amdgpu/si_dpm.h u16 soft_regs_start; soft_regs_start 985 drivers/gpu/drm/amd/amdgpu/si_dpm.h u32 soft_regs_start; soft_regs_start 245 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t soft_regs_start; soft_regs_start 1052 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t handshake_disables_offset = data->soft_regs_start soft_regs_start 1068 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t handshake_disables_offset = data->soft_regs_start soft_regs_start 1155 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->soft_regs_start + soft_regs_start 3551 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c offset = data->soft_regs_start + smum_get_offsetof(hwmgr, soft_regs_start 4098 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->soft_regs_start + smum_get_offsetof(hwmgr, soft_regs_start 4103 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->soft_regs_start + smum_get_offsetof(hwmgr, soft_regs_start 4742 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->soft_regs_start + soft_regs_start 4748 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->soft_regs_start + soft_regs_start 4754 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->soft_regs_start + soft_regs_start 4760 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->soft_regs_start + soft_regs_start 4766 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->soft_regs_start + soft_regs_start 247 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t soft_regs_start; soft_regs_start 259 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t soft_regs_start; soft_regs_start 2393 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->soft_regs_start = tmp; soft_regs_start 2394 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c ci_data->soft_regs_start = tmp; soft_regs_start 62 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h uint32_t soft_regs_start; soft_regs_start 311 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c &(priv->smu7_data.soft_regs_start), 0x40000); soft_regs_start 2471 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c data->soft_regs_start = tmp; soft_regs_start 2472 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smu7_data.soft_regs_start = tmp; soft_regs_start 253 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c &(priv->smu7_data.soft_regs_start), 0x40000); soft_regs_start 2303 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c data->soft_regs_start = tmp; soft_regs_start 2304 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu7_data->soft_regs_start = tmp; soft_regs_start 315 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c &(smu_data->smu7_data.soft_regs_start), 0x40000); soft_regs_start 1629 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start + soft_regs_start 2408 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c data->soft_regs_start = tmp; soft_regs_start 2409 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smu7_data.soft_regs_start = tmp; soft_regs_start 348 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c if (smu_data->soft_regs_start) soft_regs_start 350 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c smu_data->soft_regs_start + smum_get_offsetof(hwmgr, soft_regs_start 450 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c smu_data->soft_regs_start + smum_get_offsetof(hwmgr, soft_regs_start 44 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t soft_regs_start; soft_regs_start 220 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c &(priv->smu7_data.soft_regs_start), 0x40000); soft_regs_start 2780 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c data->soft_regs_start = tmp; soft_regs_start 2781 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smu7_data.soft_regs_start = tmp; soft_regs_start 217 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c &(smu_data->smu7_data.soft_regs_start), soft_regs_start 249 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c data->soft_regs_start = tmp; soft_regs_start 250 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smu7_data.soft_regs_start = tmp; soft_regs_start 1712 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smu7_data.soft_regs_start + soft_regs_start 1726 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smu7_data.soft_regs_start + soft_regs_start 1287 drivers/gpu/drm/radeon/ci_dpm.c pi->soft_regs_start + reg_offset, soft_regs_start 1298 drivers/gpu/drm/radeon/ci_dpm.c pi->soft_regs_start + reg_offset, soft_regs_start 1838 drivers/gpu/drm/radeon/ci_dpm.c pi->soft_regs_start = tmp; soft_regs_start 219 drivers/gpu/drm/radeon/ci_dpm.h u32 soft_regs_start; soft_regs_start 1715 drivers/gpu/drm/radeon/cypress_dpm.c pi->soft_regs_start = (u16)tmp; soft_regs_start 474 drivers/gpu/drm/radeon/kv_dpm.c pi->soft_regs_start = tmp; soft_regs_start 1340 drivers/gpu/drm/radeon/kv_dpm.c return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset, soft_regs_start 1349 drivers/gpu/drm/radeon/kv_dpm.c return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset, soft_regs_start 123 drivers/gpu/drm/radeon/kv_dpm.h u32 soft_regs_start; soft_regs_start 1125 drivers/gpu/drm/radeon/ni_dpm.c pi->soft_regs_start = (u16)tmp; soft_regs_start 240 drivers/gpu/drm/radeon/rv770_dpm.c pi->soft_regs_start + reg_offset, soft_regs_start 251 drivers/gpu/drm/radeon/rv770_dpm.c pi->soft_regs_start + reg_offset, soft_regs_start 2427 drivers/gpu/drm/radeon/rv770_dpm.c pi->soft_regs_start = RV770_SMC_SOFT_REGISTERS_START; soft_regs_start 136 drivers/gpu/drm/radeon/rv770_dpm.h u16 soft_regs_start; soft_regs_start 3190 drivers/gpu/drm/radeon/si_dpm.c si_pi->soft_regs_start + reg_offset, value, soft_regs_start 3201 drivers/gpu/drm/radeon/si_dpm.c si_pi->soft_regs_start + reg_offset, soft_regs_start 3500 drivers/gpu/drm/radeon/si_dpm.c si_pi->soft_regs_start = tmp; soft_regs_start 178 drivers/gpu/drm/radeon/si_dpm.h u32 soft_regs_start;