socfpga_clk 102 drivers/clk/socfpga/clk-gate-a10.c struct socfpga_gate_clk *socfpga_clk; socfpga_clk 108 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); socfpga_clk 109 drivers/clk/socfpga/clk-gate-a10.c if (WARN_ON(!socfpga_clk)) socfpga_clk 117 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0]; socfpga_clk 118 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk->hw.bit_idx = clk_gate[1]; socfpga_clk 126 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk->fixed_div = 0; socfpga_clk 128 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk->fixed_div = fixed_div; socfpga_clk 132 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; socfpga_clk 133 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk->shift = div_reg[1]; socfpga_clk 134 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk->width = div_reg[2]; socfpga_clk 136 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk->div_reg = NULL; socfpga_clk 141 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk->clk_phase[0] = clk_phase[0]; socfpga_clk 142 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk->clk_phase[1] = clk_phase[1]; socfpga_clk 144 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk->sys_mgr_base_addr = socfpga_clk 146 drivers/clk/socfpga/clk-gate-a10.c if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) { socfpga_clk 161 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk->hw.hw.init = &init; socfpga_clk 163 drivers/clk/socfpga/clk-gate-a10.c clk = clk_register(NULL, &socfpga_clk->hw.hw); socfpga_clk 165 drivers/clk/socfpga/clk-gate-a10.c kfree(socfpga_clk); socfpga_clk 78 drivers/clk/socfpga/clk-gate-s10.c struct socfpga_gate_clk *socfpga_clk; socfpga_clk 81 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); socfpga_clk 82 drivers/clk/socfpga/clk-gate-s10.c if (!socfpga_clk) socfpga_clk 85 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk->hw.reg = regbase + gate_reg; socfpga_clk 86 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk->hw.bit_idx = gate_idx; socfpga_clk 91 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk->fixed_div = fixed_div; socfpga_clk 94 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk->div_reg = regbase + div_reg; socfpga_clk 96 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk->div_reg = NULL; socfpga_clk 98 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk->width = div_width; socfpga_clk 99 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk->shift = div_offset; socfpga_clk 102 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk->bypass_reg = regbase + bypass_reg; socfpga_clk 104 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk->bypass_reg = NULL; socfpga_clk 105 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk->bypass_shift = bypass_shift; socfpga_clk 117 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk->hw.hw.init = &init; socfpga_clk 119 drivers/clk/socfpga/clk-gate-s10.c clk = clk_register(NULL, &socfpga_clk->hw.hw); socfpga_clk 121 drivers/clk/socfpga/clk-gate-s10.c kfree(socfpga_clk); socfpga_clk 178 drivers/clk/socfpga/clk-gate.c struct socfpga_gate_clk *socfpga_clk; socfpga_clk 185 drivers/clk/socfpga/clk-gate.c socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); socfpga_clk 186 drivers/clk/socfpga/clk-gate.c if (WARN_ON(!socfpga_clk)) socfpga_clk 198 drivers/clk/socfpga/clk-gate.c socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; socfpga_clk 199 drivers/clk/socfpga/clk-gate.c socfpga_clk->hw.bit_idx = clk_gate[1]; socfpga_clk 207 drivers/clk/socfpga/clk-gate.c socfpga_clk->fixed_div = 0; socfpga_clk 209 drivers/clk/socfpga/clk-gate.c socfpga_clk->fixed_div = fixed_div; socfpga_clk 213 drivers/clk/socfpga/clk-gate.c socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; socfpga_clk 214 drivers/clk/socfpga/clk-gate.c socfpga_clk->shift = div_reg[1]; socfpga_clk 215 drivers/clk/socfpga/clk-gate.c socfpga_clk->width = div_reg[2]; socfpga_clk 217 drivers/clk/socfpga/clk-gate.c socfpga_clk->div_reg = NULL; socfpga_clk 222 drivers/clk/socfpga/clk-gate.c socfpga_clk->clk_phase[0] = clk_phase[0]; socfpga_clk 223 drivers/clk/socfpga/clk-gate.c socfpga_clk->clk_phase[1] = clk_phase[1]; socfpga_clk 239 drivers/clk/socfpga/clk-gate.c socfpga_clk->hw.hw.init = &init; socfpga_clk 241 drivers/clk/socfpga/clk-gate.c clk = clk_register(NULL, &socfpga_clk->hw.hw); socfpga_clk 243 drivers/clk/socfpga/clk-gate.c kfree(socfpga_clk);