soc_mask          453 drivers/clk/ti/clkctrl.c 	u16 soc_mask = 0;
soc_mask          479 drivers/clk/ti/clkctrl.c 		soc_mask = CLKF_SOC_DRA72;
soc_mask          481 drivers/clk/ti/clkctrl.c 		soc_mask = CLKF_SOC_DRA74;
soc_mask          483 drivers/clk/ti/clkctrl.c 		soc_mask = CLKF_SOC_DRA76;
soc_mask          517 drivers/clk/ti/clkctrl.c 		soc_mask |= CLKF_SOC_NONSEC;
soc_mask          581 drivers/clk/ti/clkctrl.c 		    (reg_data->flags & soc_mask) == 0) {
soc_mask         1572 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	uint32_t sclk_mask, mclk_mask, soc_mask;
soc_mask         1591 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 						 &soc_mask);
soc_mask         1596 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
soc_mask         1293 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 				uint32_t *soc_mask)
soc_mask         1310 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	*soc_mask  = 0;
soc_mask         1317 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		*soc_mask  = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
soc_mask         1327 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		*soc_mask  = soc_dpm_table->count - 1;
soc_mask         4032 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
soc_mask         4041 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		*soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
soc_mask         4053 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		*soc_mask = table_info->vdd_dep_on_socclk->count - 1;
soc_mask         4143 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	uint32_t soc_mask = 0;
soc_mask         4146 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
soc_mask         4162 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
soc_mask         1583 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
soc_mask         1592 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	*soc_mask  = 0;
soc_mask         1599 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		*soc_mask  = VEGA12_UMD_PSTATE_SOCCLK_LEVEL;
soc_mask         1609 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		*soc_mask  = soc_dpm_table->count - 1;
soc_mask         1639 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	uint32_t soc_mask = 0;
soc_mask         1655 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
soc_mask         2474 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 				uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
soc_mask         2483 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	*soc_mask  = 0;
soc_mask         2490 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		*soc_mask  = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
soc_mask         2500 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		*soc_mask  = soc_dpm_table->count - 1;
soc_mask         2673 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	uint32_t sclk_mask, mclk_mask, soc_mask;
soc_mask         2692 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
soc_mask         2697 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask);
soc_mask          444 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 				      uint32_t *soc_mask);
soc_mask          674 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
soc_mask          675 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
soc_mask         1216 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 					 uint32_t *soc_mask)
soc_mask         1242 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		if(soc_mask) {
soc_mask         1246 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			*soc_mask = level_count - 1;
soc_mask         1990 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 			      uint32_t *soc_mask)
soc_mask         2006 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	*soc_mask  = 0;
soc_mask         2013 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		*soc_mask  = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
soc_mask         2023 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		*soc_mask  = soc_dpm_table->count - 1;
soc_mask         1375 drivers/pinctrl/pinctrl-single.c 		unsigned soc_mask;
soc_mask         1381 drivers/pinctrl/pinctrl-single.c 		soc_mask = pcs_soc->irq_enable_mask;
soc_mask         1385 drivers/pinctrl/pinctrl-single.c 			mask |= soc_mask;
soc_mask         1387 drivers/pinctrl/pinctrl-single.c 			mask &= ~soc_mask;