so 137 arch/ia64/include/asm/processor.h __u64 so : 1; so 10213 arch/m68k/ifpsp060/src/fplsp.S # if enabled so the operating system can log the event. # so 12044 arch/m68k/ifpsp060/src/fpsp.S # if the result would have overflowed/underflowed. If so, use unf_res() # so 20598 arch/m68k/ifpsp060/src/fpsp.S # if exp now equals one, then it overflowed so call ovf_res. so 20809 arch/m68k/ifpsp060/src/fpsp.S # if exp now equals one, then it overflowed so call ovf_res. so 7499 arch/m68k/ifpsp060/src/pfpsp.S # if exp now equals one, then it overflowed so call ovf_res. so 7710 arch/m68k/ifpsp060/src/pfpsp.S # if exp now equals one, then it overflowed so call ovf_res. so 8475 arch/m68k/ifpsp060/src/pfpsp.S # if the result would have overflowed/underflowed. If so, use unf_res() # so 127 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h # Set the SP global variable to zero so the master knows we've started so 60 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c struct sh_mobile_lcdc_sys_bus_ops *so) so 62 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c return so->read_data(sohandle); so 66 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c struct sh_mobile_lcdc_sys_bus_ops *so, so 70 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c so->write_data(sohandle, v); /* PTH4/LCDRS High [param, 17:0] */ so 72 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c so->write_index(sohandle, v); /* PTH4/LCDRS Low [cmd, 7:0] */ so 76 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c struct sh_mobile_lcdc_sys_bus_ops *so, so 82 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, data[i]); so 86 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c struct sh_mobile_lcdc_sys_bus_ops *so) so 91 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xb0); so 92 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 95 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xb1); so 96 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 99 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xbf); so 103 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c read_reg(sohandle, so); so 106 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c device_code = ((read_reg(sohandle, so) & 0xff) << 24); so 107 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c device_code |= ((read_reg(sohandle, so) & 0xff) << 16); so 108 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c device_code |= ((read_reg(sohandle, so) & 0xff) << 8); so 109 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c device_code |= (read_reg(sohandle, so) & 0xff); so 115 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c struct sh_mobile_lcdc_sys_bus_ops *so) so 117 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0x2c); so 121 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c struct sh_mobile_lcdc_sys_bus_ops *so) so 126 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_memory_start(sohandle, so); so 130 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 134 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c struct sh_mobile_lcdc_sys_bus_ops *so) so 137 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xb0); so 138 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 141 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xb1); so 142 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 145 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xb3); so 146 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_data(sohandle, so, data_frame_if, ARRAY_SIZE(data_frame_if)); so 149 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xb4); so 150 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); /* DBI, internal clock */ so 153 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xc0); so 154 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_data(sohandle, so, data_panel, ARRAY_SIZE(data_panel)); so 157 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xc1); so 158 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing)); so 161 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xc2); so 162 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing)); so 165 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xc3); so 166 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing)); so 169 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xc4); so 170 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_data(sohandle, so, data_timing_src, ARRAY_SIZE(data_timing_src)); so 173 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xc8); so 174 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma)); so 177 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xc9); so 178 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma)); so 181 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xca); so 182 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma)); so 185 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xd0); so 186 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_data(sohandle, so, data_power, ARRAY_SIZE(data_power)); so 189 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xd1); so 190 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 191 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x0f); so 192 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x02); so 195 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xd2); so 196 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x63); so 197 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x24); so 200 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xd3); so 201 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x63); so 202 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x24); so 205 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xd4); so 206 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x63); so 207 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x24); so 209 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0xd8); so 210 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x77); so 211 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x77); so 214 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0x35); so 215 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 218 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0x44); so 219 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 220 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 223 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0x2a); so 224 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 225 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 226 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 227 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0xef); so 230 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0x2b); so 231 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 232 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x00); so 233 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x01); so 234 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 1, 0x8f); so 237 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0x11); so 242 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c clear_memory(sohandle, so); so 245 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_reg(sohandle, so, 0, 0x29); so 248 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_memory_start(sohandle, so); so 251 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c int kfr2r09_lcd_setup(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so) so 263 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c if (read_device_code(sohandle, so) != 0x01221517) so 268 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c display_on(sohandle, so); so 272 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c void kfr2r09_lcd_start(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so) so 274 arch/sh/boards/mach-kfr2r09/lcd_wqvga.c write_memory_start(sohandle, so); so 113 arch/sh/boards/mach-migor/lcd_qvga.c int migor_lcd_qvga_setup(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so) so 120 arch/sh/boards/mach-migor/lcd_qvga.c migor_lcd_qvga_seq(sohandle, so, sync_data, ARRAY_SIZE(sync_data)); so 122 arch/sh/boards/mach-migor/lcd_qvga.c if (read_reg16(sohandle, so, 0) != 0x1505) so 127 arch/sh/boards/mach-migor/lcd_qvga.c migor_lcd_qvga_seq(sohandle, so, sync_data, ARRAY_SIZE(sync_data)); so 128 arch/sh/boards/mach-migor/lcd_qvga.c write_reg16(sohandle, so, 0x00A4, 0x0001); so 131 arch/sh/boards/mach-migor/lcd_qvga.c migor_lcd_qvga_seq(sohandle, so, magic0_data, ARRAY_SIZE(magic0_data)); so 134 arch/sh/boards/mach-migor/lcd_qvga.c migor_lcd_qvga_seq(sohandle, so, magic1_data, ARRAY_SIZE(magic1_data)); so 135 arch/sh/boards/mach-migor/lcd_qvga.c write_reg16(sohandle, so, 0x0050, 0xef - (yres - 1)); so 136 arch/sh/boards/mach-migor/lcd_qvga.c write_reg16(sohandle, so, 0x0051, 0x00ef); so 137 arch/sh/boards/mach-migor/lcd_qvga.c write_reg16(sohandle, so, 0x0052, 0x0000); so 138 arch/sh/boards/mach-migor/lcd_qvga.c write_reg16(sohandle, so, 0x0053, xres - 1); so 140 arch/sh/boards/mach-migor/lcd_qvga.c migor_lcd_qvga_seq(sohandle, so, magic2_data, ARRAY_SIZE(magic2_data)); so 143 arch/sh/boards/mach-migor/lcd_qvga.c migor_lcd_qvga_seq(sohandle, so, magic3_data, ARRAY_SIZE(magic3_data)); so 148 arch/sh/boards/mach-migor/lcd_qvga.c write_reg16(sohandle, so, 0x0020, 0x0000); /* horiz addr */ so 149 arch/sh/boards/mach-migor/lcd_qvga.c write_reg16(sohandle, so, 0x0021, 0x0000); /* vert addr */ so 152 arch/sh/boards/mach-migor/lcd_qvga.c write_reg16(sohandle, so, 0x0022, 0x0000); so 154 arch/sh/boards/mach-migor/lcd_qvga.c write_reg16(sohandle, so, 0x0020, 0x0000); /* reset horiz addr */ so 155 arch/sh/boards/mach-migor/lcd_qvga.c write_reg16(sohandle, so, 0x0021, 0x0000); /* reset vert addr */ so 156 arch/sh/boards/mach-migor/lcd_qvga.c write_reg16(sohandle, so, 0x0007, 0x0173); so 160 arch/sh/boards/mach-migor/lcd_qvga.c write_reg(sohandle, so, 0x00, 0x22); so 9 arch/x86/boot/code16gcc.h # gcc 4.9+ has a real -m16 option so we can drop this hack long term. so 502 crypto/twofish_common.c ctx->s[2][i] = mds[2][q1[q0[q0[(a) ^ sc] ^ sg] ^ sk] ^ so]; \ so 580 crypto/twofish_common.c u8 si = 0, sj = 0, sk = 0, sl = 0, sm = 0, sn = 0, so = 0, sp = 0; so 627 crypto/twofish_common.c CALC_S (sm, sn, so, sp, 24, 0x00, 0x2D, 0x01, 0x2D); /* 01 A4 02 A4 */ so 628 crypto/twofish_common.c CALC_S (sm, sn, so, sp, 25, 0x2D, 0xA4, 0x44, 0x8A); /* A4 56 A1 55 */ so 629 crypto/twofish_common.c CALC_S (sm, sn, so, sp, 26, 0x8A, 0xD5, 0xBF, 0xD1); /* 55 82 FC 87 */ so 630 crypto/twofish_common.c CALC_S (sm, sn, so, sp, 27, 0xD1, 0x7F, 0x3D, 0x99); /* 87 F3 C1 5A */ so 631 crypto/twofish_common.c CALC_S (sm, sn, so, sp, 28, 0x99, 0x46, 0x66, 0x96); /* 5A 1E 47 58 */ so 632 crypto/twofish_common.c CALC_S (sm, sn, so, sp, 29, 0x96, 0x3C, 0x5B, 0xED); /* 58 C6 AE DB */ so 633 crypto/twofish_common.c CALC_S (sm, sn, so, sp, 30, 0xED, 0x37, 0x4F, 0xE0); /* DB 68 3D 9E */ so 634 crypto/twofish_common.c CALC_S (sm, sn, so, sp, 31, 0xE0, 0xD0, 0x8C, 0x17); /* 9E E5 19 03 */ so 77 drivers/gpu/drm/i915/gt/intel_renderstate.c static int render_state_setup(struct intel_renderstate *so, so 80 drivers/gpu/drm/i915/gt/intel_renderstate.c const struct intel_renderstate_rodata *rodata = so->rodata; so 86 drivers/gpu/drm/i915/gt/intel_renderstate.c ret = i915_gem_object_prepare_write(so->obj, &needs_clflush); so 90 drivers/gpu/drm/i915/gt/intel_renderstate.c d = kmap_atomic(i915_gem_object_get_dirty_page(so->obj, 0)); so 96 drivers/gpu/drm/i915/gt/intel_renderstate.c u64 r = s + so->vma->node.start; so 118 drivers/gpu/drm/i915/gt/intel_renderstate.c so->batch_offset = i915_ggtt_offset(so->vma); so 119 drivers/gpu/drm/i915/gt/intel_renderstate.c so->batch_size = rodata->batch_items * sizeof(u32); so 124 drivers/gpu/drm/i915/gt/intel_renderstate.c so->aux_offset = i * sizeof(u32); so 154 drivers/gpu/drm/i915/gt/intel_renderstate.c so->aux_size = i * sizeof(u32) - so->aux_offset; so 155 drivers/gpu/drm/i915/gt/intel_renderstate.c so->aux_offset += so->batch_offset; so 160 drivers/gpu/drm/i915/gt/intel_renderstate.c so->aux_size = ALIGN(so->aux_size, 8); so 168 drivers/gpu/drm/i915/gt/intel_renderstate.c i915_gem_object_finish_access(so->obj); so 182 drivers/gpu/drm/i915/gt/intel_renderstate.c struct intel_renderstate so = {}; /* keep the compiler happy */ so 185 drivers/gpu/drm/i915/gt/intel_renderstate.c so.rodata = render_state_get_rodata(engine); so 186 drivers/gpu/drm/i915/gt/intel_renderstate.c if (!so.rodata) so 189 drivers/gpu/drm/i915/gt/intel_renderstate.c if (so.rodata->batch_items * 4 > PAGE_SIZE) so 192 drivers/gpu/drm/i915/gt/intel_renderstate.c so.obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); so 193 drivers/gpu/drm/i915/gt/intel_renderstate.c if (IS_ERR(so.obj)) so 194 drivers/gpu/drm/i915/gt/intel_renderstate.c return PTR_ERR(so.obj); so 196 drivers/gpu/drm/i915/gt/intel_renderstate.c so.vma = i915_vma_instance(so.obj, &engine->gt->ggtt->vm, NULL); so 197 drivers/gpu/drm/i915/gt/intel_renderstate.c if (IS_ERR(so.vma)) { so 198 drivers/gpu/drm/i915/gt/intel_renderstate.c err = PTR_ERR(so.vma); so 202 drivers/gpu/drm/i915/gt/intel_renderstate.c err = i915_vma_pin(so.vma, 0, 0, PIN_GLOBAL | PIN_HIGH); so 206 drivers/gpu/drm/i915/gt/intel_renderstate.c err = render_state_setup(&so, rq->i915); so 211 drivers/gpu/drm/i915/gt/intel_renderstate.c so.batch_offset, so.batch_size, so 216 drivers/gpu/drm/i915/gt/intel_renderstate.c if (so.aux_size > 8) { so 218 drivers/gpu/drm/i915/gt/intel_renderstate.c so.aux_offset, so.aux_size, so 224 drivers/gpu/drm/i915/gt/intel_renderstate.c i915_vma_lock(so.vma); so 225 drivers/gpu/drm/i915/gt/intel_renderstate.c err = i915_request_await_object(rq, so.vma->obj, false); so 227 drivers/gpu/drm/i915/gt/intel_renderstate.c err = i915_vma_move_to_active(so.vma, rq, 0); so 228 drivers/gpu/drm/i915/gt/intel_renderstate.c i915_vma_unlock(so.vma); so 230 drivers/gpu/drm/i915/gt/intel_renderstate.c i915_vma_unpin(so.vma); so 232 drivers/gpu/drm/i915/gt/intel_renderstate.c i915_vma_close(so.vma); so 234 drivers/gpu/drm/i915/gt/intel_renderstate.c i915_gem_object_put(so.obj); so 2592 drivers/platform/x86/thinkpad_acpi.c unsigned int si, so; so 2603 drivers/platform/x86/thinkpad_acpi.c so = 0; so 2615 drivers/platform/x86/thinkpad_acpi.c hotkey_read_nvram(&s[so], poll_mask); so 2634 drivers/platform/x86/thinkpad_acpi.c si = so; so 2646 drivers/platform/x86/thinkpad_acpi.c if (likely(si != so)) { so 2647 drivers/platform/x86/thinkpad_acpi.c hotkey_compare_and_issue_event(&s[so], &s[si], so 2652 drivers/platform/x86/thinkpad_acpi.c so = si; so 613 fs/nfsd/nfs4callback.c static void encode_stateowner(struct xdr_stream *xdr, struct nfs4_stateowner *so) so 617 fs/nfsd/nfs4callback.c p = xdr_reserve_space(xdr, 8 + 4 + so->so_owner.len); so 618 fs/nfsd/nfs4callback.c p = xdr_encode_opaque_fixed(p, &so->so_client->cl_clientid, 8); so 619 fs/nfsd/nfs4callback.c xdr_encode_opaque(p, so->so_owner.data, so->so_owner.len); so 375 fs/nfsd/nfs4state.c struct nfs4_stateowner *so; so 379 fs/nfsd/nfs4state.c list_for_each_entry(so, &clp->cl_ownerstr_hashtbl[hashval], so 381 fs/nfsd/nfs4state.c if (!so->so_is_open_owner) so 383 fs/nfsd/nfs4state.c if (same_owner_str(so, &open->op_owner)) so 384 fs/nfsd/nfs4state.c return openowner(nfs4_get_stateowner(so)); so 1499 fs/nfsd/nfs4state.c struct nfs4_stateowner *so = cstate->replay_owner; so 1508 fs/nfsd/nfs4state.c if (!so) so 1510 fs/nfsd/nfs4state.c if (so->so_is_open_owner) so 1511 fs/nfsd/nfs4state.c release_last_closed_stateid(openowner(so)); so 1512 fs/nfsd/nfs4state.c so->so_seqid++; so 2034 fs/nfsd/nfs4state.c struct nfs4_stateowner *so, *tmp; so 2036 fs/nfsd/nfs4state.c list_for_each_entry_safe(so, tmp, &clp->cl_ownerstr_hashtbl[i], so 2039 fs/nfsd/nfs4state.c WARN_ON_ONCE(so->so_is_open_owner); so 2040 fs/nfsd/nfs4state.c remove_blocked_locks(lockowner(so)); so 4035 fs/nfsd/nfs4state.c struct nfs4_stateowner *so) so 4038 fs/nfsd/nfs4state.c mutex_lock(&so->so_replay.rp_mutex); so 4039 fs/nfsd/nfs4state.c cstate->replay_owner = nfs4_get_stateowner(so); so 4045 fs/nfsd/nfs4state.c struct nfs4_stateowner *so = cstate->replay_owner; so 4047 fs/nfsd/nfs4state.c if (so != NULL) { so 4049 fs/nfsd/nfs4state.c mutex_unlock(&so->so_replay.rp_mutex); so 4050 fs/nfsd/nfs4state.c nfs4_put_stateowner(so); so 4084 fs/nfsd/nfs4state.c static void nfs4_unhash_openowner(struct nfs4_stateowner *so) so 4086 fs/nfsd/nfs4state.c unhash_openowner_locked(openowner(so)); so 4089 fs/nfsd/nfs4state.c static void nfs4_free_openowner(struct nfs4_stateowner *so) so 4091 fs/nfsd/nfs4state.c struct nfs4_openowner *oo = openowner(so); so 4482 fs/nfsd/nfs4state.c static __be32 nfsd4_check_seqid(struct nfsd4_compound_state *cstate, struct nfs4_stateowner *so, u32 seqid) so 4486 fs/nfsd/nfs4state.c if (seqid == so->so_seqid - 1) so 4488 fs/nfsd/nfs4state.c if (seqid == so->so_seqid) so 5114 fs/nfsd/nfs4state.c struct nfs4_stateowner *so = &open->op_openowner->oo_owner; so 5116 fs/nfsd/nfs4state.c nfsd4_cstate_assign_replay(cstate, so); so 5117 fs/nfsd/nfs4state.c nfs4_put_stateowner(so); so 6174 fs/nfsd/nfs4state.c struct nfs4_stateowner *so; so 6178 fs/nfsd/nfs4state.c list_for_each_entry(so, &clp->cl_ownerstr_hashtbl[strhashval], so 6180 fs/nfsd/nfs4state.c if (so->so_is_open_owner) so 6182 fs/nfsd/nfs4state.c if (same_owner_str(so, owner)) so 6183 fs/nfsd/nfs4state.c return lockowner(nfs4_get_stateowner(so)); so 4433 fs/nfsd/nfs4xdr.c struct nfs4_stateowner *so = resp->cstate.replay_owner; so 4489 fs/nfsd/nfs4xdr.c if (so) { so 4492 fs/nfsd/nfs4xdr.c so->so_replay.rp_status = op->status; so 4493 fs/nfsd/nfs4xdr.c so->so_replay.rp_buflen = len; so 4495 fs/nfsd/nfs4xdr.c so->so_replay.rp_buf, len); so 466 fs/nfsd/state.h static inline struct nfs4_openowner * openowner(struct nfs4_stateowner *so) so 468 fs/nfsd/state.h return container_of(so, struct nfs4_openowner, oo_owner); so 471 fs/nfsd/state.h static inline struct nfs4_lockowner * lockowner(struct nfs4_stateowner *so) so 473 fs/nfsd/state.h return container_of(so, struct nfs4_lockowner, lo_owner); so 1122 fs/xfs/libxfs/xfs_format.h #define XFS_SUMPTR(mp,bp,so) \ so 1124 fs/xfs/libxfs/xfs_format.h (((so) * (uint)sizeof(xfs_suminfo_t)) & XFS_BLOCKMASK(mp)))) so 457 fs/xfs/libxfs/xfs_rtbitmap.c int so; /* index into the summary file */ so 463 fs/xfs/libxfs/xfs_rtbitmap.c so = XFS_SUMOFFS(mp, log, bbno); so 467 fs/xfs/libxfs/xfs_rtbitmap.c sb = XFS_SUMOFFSTOBLOCK(mp, so); so 495 fs/xfs/libxfs/xfs_rtbitmap.c sp = XFS_SUMPTR(mp, bp, so); so 1350 net/sunrpc/svcsock.c struct socket *so = sockfd_lookup(fd, &err); so 1356 net/sunrpc/svcsock.c if (!so) so 1359 net/sunrpc/svcsock.c if ((so->sk->sk_family != PF_INET) && (so->sk->sk_family != PF_INET6)) so 1362 net/sunrpc/svcsock.c if (so->sk->sk_protocol != IPPROTO_TCP && so 1363 net/sunrpc/svcsock.c so->sk->sk_protocol != IPPROTO_UDP) so 1366 net/sunrpc/svcsock.c if (so->state > SS_UNCONNECTED) so 1371 net/sunrpc/svcsock.c svsk = svc_setup_socket(serv, so, SVC_SOCK_DEFAULTS); so 1384 net/sunrpc/svcsock.c sockfd_put(so); so 915 scripts/kconfig/symbol.c off_t so, eo; so 937 scripts/kconfig/symbol.c exact1 = (s1->eo - s1->so) == strlen(s1->sym->name); so 938 scripts/kconfig/symbol.c exact2 = (s2->eo - s2->so) == strlen(s2->sym->name); so 980 scripts/kconfig/symbol.c sym_match_arr[cnt].so = match[0].rm_so; so 2636 tools/power/x86/turbostat/turbostat.c int so, shift, sib_core; so 2660 tools/power/x86/turbostat/turbostat.c so = shift + offset; so 2661 tools/power/x86/turbostat/turbostat.c sib_core = get_core_id(so); so 2663 tools/power/x86/turbostat/turbostat.c CPU_SET_S(so, size, thiscpu->put_ids); so 2664 tools/power/x86/turbostat/turbostat.c if ((so != cpu) && so 2665 tools/power/x86/turbostat/turbostat.c (cpus[so].thread_id < 0)) so 2666 tools/power/x86/turbostat/turbostat.c cpus[so].thread_id =