snpcr            3685 drivers/gpu/drm/i915/i915_debugfs.c 	u32 snpcr = 0;
snpcr            3691 drivers/gpu/drm/i915/i915_debugfs.c 		snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
snpcr            3693 drivers/gpu/drm/i915/i915_debugfs.c 	*val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
snpcr            3712 drivers/gpu/drm/i915/i915_debugfs.c 		u32 snpcr;
snpcr            3715 drivers/gpu/drm/i915/i915_debugfs.c 		snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
snpcr            3716 drivers/gpu/drm/i915/i915_debugfs.c 		snpcr &= ~GEN6_MBC_SNPCR_MASK;
snpcr            3717 drivers/gpu/drm/i915/i915_debugfs.c 		snpcr |= val << GEN6_MBC_SNPCR_SHIFT;
snpcr            3718 drivers/gpu/drm/i915/i915_debugfs.c 		I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
snpcr            9398 drivers/gpu/drm/i915/intel_pm.c 	u32 snpcr;
snpcr            9480 drivers/gpu/drm/i915/intel_pm.c 	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
snpcr            9481 drivers/gpu/drm/i915/intel_pm.c 	snpcr &= ~GEN6_MBC_SNPCR_MASK;
snpcr            9482 drivers/gpu/drm/i915/intel_pm.c 	snpcr |= GEN6_MBC_SNPCR_MED;
snpcr            9483 drivers/gpu/drm/i915/intel_pm.c 	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);