smu_data          234 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data          243 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		smu_data->power_tune_defaults = &defaults_hawaii_pro;
smu_data          247 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		smu_data->power_tune_defaults = &defaults_hawaii_xt;
smu_data          253 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		smu_data->power_tune_defaults = &defaults_saturn_xt;
smu_data          270 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		smu_data->power_tune_defaults = &defaults_bonaire_xt;
smu_data          473 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data          476 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t array = smu_data->dpm_table_start +
smu_data          481 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			smu_data->smc_state_table.GraphicsLevel;
smu_data          491 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
smu_data          493 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark =
smu_data          497 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
smu_data          499 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
smu_data          513 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data          514 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          516 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
smu_data          517 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc;
smu_data          518 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
smu_data          519 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
smu_data          527 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data          528 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          531 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->power_tune_table.TDC_VDDC_PkgLimit =
smu_data          533 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
smu_data          535 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
smu_data          542 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data          543 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          554 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
smu_data          562 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data          570 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->power_tune_table.FuzzyFan_PwmSetDelta = CONVERT_FROM_HOST_TO_SMC_US(tmp);
smu_data          578 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data          579 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
smu_data          580 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
smu_data          581 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint8_t *hi2_vid = smu_data->power_tune_table.BapmVddCVidHiSidd2;
smu_data          607 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data          608 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint8_t *vid = smu_data->power_tune_table.VddCVid;
smu_data          623 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data          624 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	u8 *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
smu_data          625 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	u8 *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
smu_data          647 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->power_tune_table.GnbLPMLMaxVid = (u8)max;
smu_data          648 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->power_tune_table.GnbLPMLMinVid = (u8)min;
smu_data          655 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data          656 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
smu_data          657 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
smu_data          663 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
smu_data          665 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
smu_data          673 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data          707 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				(uint8_t *)&smu_data->power_tune_table,
smu_data          715 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data          717 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          718 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	SMU7_Discrete_DpmTable  *dpm_table = &(smu_data->smc_state_table);
smu_data          999 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data         1013 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->smc_state_table.LinkLevelCount =
smu_data         1301 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data         1307 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
smu_data         1309 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
smu_data         1318 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			&(smu_data->smc_state_table.MemoryLevel[i]));
smu_data         1323 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
smu_data         1329 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		smu_data->smc_state_table.MemoryLevel[1].MinVddci =
smu_data         1330 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				smu_data->smc_state_table.MemoryLevel[0].MinVddci;
smu_data         1331 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		smu_data->smc_state_table.MemoryLevel[1].MinMvdd =
smu_data         1332 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				smu_data->smc_state_table.MemoryLevel[0].MinMvdd;
smu_data         1334 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
smu_data         1335 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
smu_data         1337 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
smu_data         1339 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
smu_data         1651 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data         1673 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				smu_data->arb_table_start,
smu_data         1688 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data         1696 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			(uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
smu_data         1699 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		smu_data->smc_state_table.GraphicsBootLevel = 0;
smu_data         1706 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		(uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
smu_data         1709 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		smu_data->smc_state_table.MemoryBootLevel = 0;
smu_data         1724 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smu_backend;
smu_data         1728 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
smu_data         1729 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if (smu_data->mc_reg_table.validflag & 1<<j) {
smu_data         1733 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
smu_data         1735 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
smu_data         1766 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data         1769 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
smu_data         1771 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
smu_data         1776 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
smu_data         1779 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	ci_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
smu_data         1780 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				mc_reg_table_data, smu_data->mc_reg_table.last,
smu_data         1781 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				smu_data->mc_reg_table.validflag);
smu_data         1810 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data         1819 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	memset(&smu_data->mc_regs, 0, sizeof(SMU7_Discrete_MCRegisters));
smu_data         1821 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
smu_data         1826 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]);
smu_data         1829 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				 (uint8_t *)&smu_data->mc_regs.data[0],
smu_data         1837 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data         1839 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters));
smu_data         1840 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
smu_data         1844 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
smu_data         1848 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	return ci_copy_bytes_to_smc(hwmgr, smu_data->mc_reg_table_start,
smu_data         1849 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			(uint8_t *)&smu_data->mc_regs, sizeof(SMU7_Discrete_MCRegisters), SMC_RAM_END);
smu_data         1855 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data         1863 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			smu_data->smc_state_table.GraphicsBootLevel = level;
smu_data         1873 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			smu_data->smc_state_table.MemoryBootLevel = level;
smu_data         1944 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data         1945 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	SMU7_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
smu_data         1950 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
smu_data         2101 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_copy_bytes_to_smc(hwmgr, smu_data->dpm_table_start +
smu_data         2212 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data         2227 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				smu_data->dpm_table_start +
smu_data         2676 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
smu_data         2678 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_mc_reg_table *ni_table = &smu_data->mc_reg_table;
smu_data         2761 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)
smu_data         2765 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			smu_data->smc_state_table.GraphicsLevel;
smu_data         2766 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t array = smu_data->dpm_table_start +
smu_data         2769 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t mclk_array = smu_data->dpm_table_start +
smu_data         2772 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			smu_data->smc_state_table.MemoryLevel;
smu_data         2784 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
smu_data         2819 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
smu_data         2857 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = hwmgr->smu_backend;
smu_data         2869 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		smu_data->smc_state_table.UvdBootLevel = 0;
smu_data         2871 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		smu_data->smc_state_table.UvdBootLevel = uvd_table->count - 1;
smu_data         2874 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				UvdBootLevel, smu_data->smc_state_table.UvdBootLevel);
smu_data          203 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
smu_data          205 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (0 != smu_data->avfs_btc_param) {
smu_data          207 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param)) {
smu_data          471 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data          478 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->power_tune_defaults =
smu_data          482 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->power_tune_defaults = &fiji_power_tune_data_set_array[0];
smu_data          489 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data          490 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          492 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	SMU73_Discrete_DpmTable  *dpm_table = &(smu_data->smc_state_table);
smu_data          572 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data          573 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          575 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
smu_data          576 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
smu_data          577 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
smu_data          578 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
smu_data          587 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data          590 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          596 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->power_tune_table.TDC_VDDC_PkgLimit =
smu_data          598 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
smu_data          600 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
smu_data          607 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data          608 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          619 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
smu_data          620 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->power_tune_table.LPMLTemperatureMin =
smu_data          622 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->power_tune_table.LPMLTemperatureMax =
smu_data          624 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
smu_data          632 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data          636 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
smu_data          643 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data          653 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->power_tune_table.FuzzyFan_PwmSetDelta =
smu_data          662 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data          666 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->power_tune_table.GnbLPML[i] = 0;
smu_data          673 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data          676 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
smu_data          677 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
smu_data          683 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
smu_data          685 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
smu_data          694 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data          747 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				(uint8_t *)&smu_data->power_tune_table,
smu_data          833 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data          849 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->smc_state_table.LinkLevelCount =
smu_data         1006 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data         1014 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu_data         1019 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smu_data->smc_state_table.GraphicsLevel;
smu_data         1045 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->smc_state_table.GraphicsDpmLevelCount =
smu_data         1226 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data         1230 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu_data         1235 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smu_data->smc_state_table.MemoryLevel;
smu_data         1260 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->smc_state_table.MemoryDpmLevelCount =
smu_data         1532 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data         1551 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				smu_data->smu7_data.arb_table_start,
smu_data         1640 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data         1649 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smu_data->smc_state_table.GraphicsBootLevel = level;
smu_data         1658 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smu_data->smc_state_table.MemoryBootLevel = level;
smu_data         1671 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data         1703 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
smu_data         1707 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
smu_data         1718 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
smu_data         1746 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
smu_data         1748 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
smu_data         1750 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table.
smu_data         1751 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
smu_data         1766 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
smu_data         1768 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
smu_data         1770 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
smu_data         1772 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
smu_data         1783 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smc_state_table.ClockStretcherDataTable.
smu_data         1786 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smc_state_table.ClockStretcherDataTable.
smu_data         1792 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) {
smu_data         1795 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 					smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
smu_data         1808 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smu_data->smc_state_table.ClockStretcherDataTable.
smu_data         1811 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.
smu_data         1869 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data         1882 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
smu_data         1891 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smu_data->smu7_data.arb_table_start,  tmp, SMC_RAM_END);
smu_data         1927 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data         1930 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table);
smu_data         2110 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smu_data->smu7_data.dpm_table_start +
smu_data         2135 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data         2151 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (smu_data->smu7_data.fan_table_start == 0) {
smu_data         2217 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
smu_data         2267 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data         2282 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				smu_data->smu7_data.dpm_table_start +
smu_data         2370 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data         2375 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu_data->smc_state_table.UvdBootLevel = 0;
smu_data         2377 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smc_state_table.UvdBootLevel =
smu_data         2379 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable,
smu_data         2386 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
smu_data         2396 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
smu_data         2402 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data         2409 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smc_state_table.VceBootLevel =
smu_data         2412 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smc_state_table.VceBootLevel = 0;
smu_data         2414 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
smu_data         2421 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
smu_data         2428 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
smu_data         2450 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
smu_data         2461 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smu7_data.dpm_table_start = tmp;
smu_data         2472 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smu7_data.soft_regs_start = tmp;
smu_data         2483 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smu7_data.mc_reg_table_start = tmp;
smu_data         2491 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smu7_data.fan_table_start = tmp;
smu_data         2501 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smu7_data.arb_table_start = tmp;
smu_data         2553 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)
smu_data         2557 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smu_data->smc_state_table.GraphicsLevel;
smu_data         2558 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu_data         2561 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
smu_data         2564 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smu_data->smc_state_table.MemoryLevel;
smu_data         2576 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
smu_data         2611 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
smu_data          282 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data          291 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu_data->power_tune_defaults = &defaults_icelandxt;
smu_data          296 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu_data->power_tune_defaults = &defaults_icelandpro;
smu_data          299 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu_data->power_tune_defaults = &defaults_iceland;
smu_data          308 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data          309 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          311 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
smu_data          312 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc;
smu_data          313 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
smu_data          314 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
smu_data          322 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data          323 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          326 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->power_tune_table.TDC_VDDC_PkgLimit =
smu_data          328 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
smu_data          330 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
smu_data          337 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data          338 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          349 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
smu_data          362 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data          366 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu_data->power_tune_table.GnbLPML[i] = 0;
smu_data          373 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data          374 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
smu_data          375 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
smu_data          381 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
smu_data          383 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
smu_data          392 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data          393 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
smu_data          394 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
smu_data          418 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data          419 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint8_t *vid = smu_data->power_tune_table.VddCVid;
smu_data          437 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data          497 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				(uint8_t *)&smu_data->power_tune_table,
smu_data          768 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data          787 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->smc_state_table.LinkLevelCount =
smu_data          962 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data          964 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start +
smu_data          970 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
smu_data          983 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 					&(smu_data->smc_state_table.GraphicsLevel[i]));
smu_data          989 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
smu_data          993 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
smu_data          997 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
smu_data         1000 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->smc_state_table.GraphicsDpmLevelCount =
smu_data         1027 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
smu_data         1031 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
smu_data         1034 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
smu_data         1349 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data         1354 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel);
smu_data         1356 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
smu_data         1365 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			&(smu_data->smc_state_table.MemoryLevel[i]));
smu_data         1372 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
smu_data         1379 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
smu_data         1380 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
smu_data         1382 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
smu_data         1385 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
smu_data         1614 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data         1637 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				smu_data->smu7_data.arb_table_start,
smu_data         1652 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data         1659 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			(uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
smu_data         1662 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu_data->smc_state_table.GraphicsBootLevel = 0;
smu_data         1669 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		(uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
smu_data         1672 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu_data->smc_state_table.MemoryBootLevel = 0;
smu_data         1691 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smu_backend;
smu_data         1695 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
smu_data         1696 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (smu_data->mc_reg_table.validflag & 1<<j) {
smu_data         1700 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
smu_data         1702 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
smu_data         1733 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data         1736 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
smu_data         1738 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
smu_data         1743 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
smu_data         1746 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	iceland_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
smu_data         1747 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				mc_reg_table_data, smu_data->mc_reg_table.last,
smu_data         1748 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				smu_data->mc_reg_table.validflag);
smu_data         1777 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data         1786 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	memset(&smu_data->mc_regs, 0, sizeof(SMU71_Discrete_MCRegisters));
smu_data         1788 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
smu_data         1794 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
smu_data         1797 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				 (uint8_t *)&smu_data->mc_regs.data[0],
smu_data         1805 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data         1807 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters));
smu_data         1808 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
smu_data         1812 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
smu_data         1816 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
smu_data         1817 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			(uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END);
smu_data         1823 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data         1831 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			smu_data->smc_state_table.GraphicsBootLevel = level;
smu_data         1841 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			smu_data->smc_state_table.MemoryBootLevel = level;
smu_data         1852 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data         1853 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data         1854 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	SMU71_Discrete_DpmTable  *dpm_table = &(smu_data->smc_state_table);
smu_data         1933 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data         1934 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	SMU71_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
smu_data         1938 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
smu_data         1958 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		result = iceland_populate_ulv_state(hwmgr, &(smu_data->ulv_setting));
smu_data         2057 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start +
smu_data         2068 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			smu_data->smu7_data.ulv_setting_starts,
smu_data         2069 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			(uint8_t *)&(smu_data->ulv_setting),
smu_data         2177 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data         2192 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				smu_data->smu7_data.dpm_table_start +
smu_data         2605 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
smu_data         2607 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table;
smu_data           99 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
smu_data          101 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (0 != smu_data->avfs_btc_param) {
smu_data          102 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param)) {
smu_data          107 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (smu_data->avfs_btc_param > 1) {
smu_data          176 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
smu_data          185 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (smu_data->avfs_btc_param > 1) {
smu_data          294 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          298 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
smu_data          299 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
smu_data          302 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (smu_data->protected_mode == 0)
smu_data          315 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 					&(smu_data->smu7_data.soft_regs_start), 0x40000);
smu_data          336 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data;
smu_data          338 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
smu_data          339 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (smu_data == NULL)
smu_data          342 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	hwmgr->smu_backend = smu_data;
smu_data          345 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		kfree(smu_data);
smu_data          426 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          428 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          429 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
smu_data          474 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          475 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          477 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
smu_data          478 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
smu_data          479 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
smu_data          480 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
smu_data          488 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          491 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          494 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->power_tune_table.TDC_VDDC_PkgLimit =
smu_data          496 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
smu_data          498 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
smu_data          505 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          506 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data          517 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
smu_data          518 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->power_tune_table.LPMLTemperatureMin =
smu_data          520 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->power_tune_table.LPMLTemperatureMax =
smu_data          522 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
smu_data          530 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          534 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
smu_data          541 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          549 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
smu_data          557 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          561 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->power_tune_table.GnbLPML[i] = 0;
smu_data          568 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          571 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
smu_data          572 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
smu_data          578 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
smu_data          580 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
smu_data          588 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          637 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				(uint8_t *)&smu_data->power_tune_table,
smu_data          770 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          787 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->smc_state_table.LinkLevelCount =
smu_data          801 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          825 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
smu_data          826 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
smu_data          844 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          845 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
smu_data          874 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (clock > smu_data->range_table[i].trans_lower_frequency
smu_data          875 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		&& clock <= smu_data->range_table[i].trans_upper_frequency) {
smu_data          980 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data          987 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu_data          992 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smc_state_table.GraphicsLevel;
smu_data          999 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
smu_data         1005 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				&(smu_data->smc_state_table.GraphicsLevel[i]));
smu_data         1015 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
smu_data         1017 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
smu_data         1018 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->smc_state_table.GraphicsDpmLevelCount =
smu_data         1127 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         1131 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu_data         1136 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smc_state_table.MemoryLevel;
smu_data         1162 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->smc_state_table.MemoryDpmLevelCount =
smu_data         1365 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         1385 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smu7_data.arb_table_start,
smu_data         1484 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         1494 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smc_state_table.GraphicsBootLevel = level;
smu_data         1503 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smc_state_table.MemoryBootLevel = level;
smu_data         1514 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         1557 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
smu_data         1575 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
smu_data         1578 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
smu_data         1599 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         1629 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
smu_data         1643 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         1646 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
smu_data         1778 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         1791 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
smu_data         1800 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
smu_data         1805 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         1812 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->power_tune_defaults =
smu_data         1816 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
smu_data         1824 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         1828 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
smu_data         1989 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], &dividers);
smu_data         2014 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smu7_data.dpm_table_start +
smu_data         2067 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         2082 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (smu_data->smu7_data.fan_table_start == 0) {
smu_data         2152 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
smu_data         2179 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         2184 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu_data->smc_state_table.UvdBootLevel = 0;
smu_data         2186 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smc_state_table.UvdBootLevel =
smu_data         2188 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
smu_data         2195 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
smu_data         2205 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
smu_data         2211 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         2218 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smc_state_table.VceBootLevel =
smu_data         2221 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smc_state_table.VceBootLevel = 0;
smu_data         2223 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
smu_data         2230 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
smu_data         2237 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
smu_data         2243 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         2254 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
smu_data         2278 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         2293 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				smu_data->smu7_data.dpm_table_start +
smu_data         2386 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
smu_data         2398 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smu7_data.dpm_table_start = tmp;
smu_data         2409 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smu7_data.soft_regs_start = tmp;
smu_data         2420 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smu7_data.mc_reg_table_start = tmp;
smu_data         2428 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smu7_data.fan_table_start = tmp;
smu_data         2438 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smu7_data.arb_table_start = tmp;
smu_data         2466 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
smu_data         2470 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smc_state_table.GraphicsLevel;
smu_data         2471 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu_data         2474 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
smu_data         2477 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smc_state_table.MemoryLevel;
smu_data         2489 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
smu_data         2524 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
smu_data          342 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
smu_data          348 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	if (smu_data->soft_regs_start)
smu_data          350 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 					smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
smu_data          358 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 						upper_32_bits(smu_data->smu_buffer.mc_addr));
smu_data          361 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 						lower_32_bits(smu_data->smu_buffer.mc_addr));
smu_data          382 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	if (!smu_data->toc) {
smu_data          385 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		smu_data->toc = kzalloc(sizeof(struct SMU_DRAMData_TOC), GFP_KERNEL);
smu_data          386 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		if (!smu_data->toc)
smu_data          388 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		toc = smu_data->toc;
smu_data          424 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	memcpy_toio(smu_data->header_buffer.kaddr, smu_data->toc,
smu_data          426 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data->header_buffer.mc_addr));
smu_data          427 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, lower_32_bits(smu_data->header_buffer.mc_addr));
smu_data          438 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	kfree(smu_data->toc);
smu_data          439 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	smu_data->toc = NULL;
smu_data          446 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
smu_data          450 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 					smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
smu_data          484 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
smu_data          488 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	if (smu_data->security_hard_key == 1)
smu_data          545 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	struct smu7_smumgr *smu_data;
smu_data          548 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
smu_data          549 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	smu_data->header_buffer.data_size =
smu_data          555 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		smu_data->header_buffer.data_size,
smu_data          558 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		&smu_data->header_buffer.handle,
smu_data          559 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		&smu_data->header_buffer.mc_addr,
smu_data          560 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		&smu_data->header_buffer.kaddr);
smu_data          568 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	smu_data->smu_buffer.data_size = 200*4096;
smu_data          570 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		smu_data->smu_buffer.data_size,
smu_data          573 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		&smu_data->smu_buffer.handle,
smu_data          574 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		&smu_data->smu_buffer.mc_addr,
smu_data          575 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		&smu_data->smu_buffer.kaddr);
smu_data          578 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		amdgpu_bo_free_kernel(&smu_data->header_buffer.handle,
smu_data          579 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 					&smu_data->header_buffer.mc_addr,
smu_data          580 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 					&smu_data->header_buffer.kaddr);
smu_data          594 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
smu_data          596 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	amdgpu_bo_free_kernel(&smu_data->header_buffer.handle,
smu_data          597 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 					&smu_data->header_buffer.mc_addr,
smu_data          598 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 					&smu_data->header_buffer.kaddr);
smu_data          601 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		amdgpu_bo_free_kernel(&smu_data->smu_buffer.handle,
smu_data          602 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 					&smu_data->smu_buffer.mc_addr,
smu_data          603 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 					&smu_data->smu_buffer.kaddr);
smu_data          606 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	kfree(smu_data->toc);
smu_data          607 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	smu_data->toc = NULL;
smu_data          511 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
smu_data          530 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.LinkLevelCount =
smu_data          689 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
smu_data          694 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t level_array_address = smu_data->smu7_data.dpm_table_start +
smu_data          700 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
smu_data          713 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 					&(smu_data->smc_state_table.GraphicsLevel[i]));
smu_data          719 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
smu_data          723 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
smu_data          727 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
smu_data          730 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.GraphicsDpmLevelCount =
smu_data          741 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
smu_data          771 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
smu_data          774 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
smu_data          777 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
smu_data         1089 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         1096 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				smu_data->smu7_data.dpm_table_start +
smu_data         1102 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				smu_data->smc_state_table.MemoryLevel;
smu_data         1114 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				&(smu_data->smc_state_table.MemoryLevel[i]));
smu_data         1120 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
smu_data         1127 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
smu_data         1128 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
smu_data         1130 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
smu_data         1133 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
smu_data         1177 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         1192 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smu_data->smc_state_table.GraphicsLevel[0].MinVoltage;
smu_data         1242 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			    smu_data->smc_state_table.MemoryLevel[0].MinVoltage;
smu_data         1489 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         1512 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				smu_data->smu7_data.arb_table_start,
smu_data         1527 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         1535 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	(uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
smu_data         1538 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smc_state_table.GraphicsBootLevel = 0;
smu_data         1547 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		(uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
smu_data         1550 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smc_state_table.MemoryBootLevel = 0;
smu_data         1578 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         1616 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
smu_data         1621 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
smu_data         1641 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
smu_data         1669 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
smu_data         1671 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
smu_data         1673 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table.
smu_data         1674 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
smu_data         1689 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
smu_data         1691 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
smu_data         1693 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
smu_data         1695 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
smu_data         1706 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smc_state_table.ClockStretcherDataTable.
smu_data         1709 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smc_state_table.ClockStretcherDataTable.
smu_data         1715 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) {
smu_data         1718 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 					smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
smu_data         1729 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smu_data->smc_state_table.ClockStretcherDataTable.
smu_data         1732 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.
smu_data         1799 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
smu_data         1813 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
smu_data         1822 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
smu_data         1828 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         1830 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data         1831 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	SMU72_Discrete_DpmTable  *dpm_table = &(smu_data->smc_state_table);
smu_data         1875 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         1877 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data         1879 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
smu_data         1880 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddC;
smu_data         1881 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
smu_data         1882 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
smu_data         1890 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         1892 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data         1900 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->power_tune_table.TDC_VDDC_PkgLimit =
smu_data         1902 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
smu_data         1904 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
smu_data         1911 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         1913 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data         1925 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
smu_data         1933 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         1938 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
smu_data         1945 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
smu_data         1954 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->power_tune_table.FuzzyFan_PwmSetDelta =
smu_data         1963 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         1968 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->power_tune_table.GnbLPML[i] = 0;
smu_data         1975 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         1979 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
smu_data         1980 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
smu_data         1986 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
smu_data         1988 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
smu_data         1996 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         2054 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(uint8_t *)&smu_data->power_tune_table,
smu_data         2066 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smu_backend;
smu_data         2070 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
smu_data         2071 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (smu_data->mc_reg_table.validflag & 1<<j) {
smu_data         2078 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
smu_data         2080 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
smu_data         2112 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
smu_data         2115 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
smu_data         2117 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
smu_data         2122 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
smu_data         2125 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	tonga_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
smu_data         2126 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				mc_reg_table_data, smu_data->mc_reg_table.last,
smu_data         2127 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				smu_data->mc_reg_table.validflag);
smu_data         2156 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
smu_data         2165 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	memset(&smu_data->mc_regs, 0, sizeof(SMU72_Discrete_MCRegisters));
smu_data         2167 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
smu_data         2173 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	address = smu_data->smu7_data.mc_reg_table_start +
smu_data         2178 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(uint8_t *)&smu_data->mc_regs.data[0],
smu_data         2187 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
smu_data         2189 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters));
smu_data         2190 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
smu_data         2195 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
smu_data         2200 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
smu_data         2201 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(uint8_t *)&smu_data->mc_regs, sizeof(SMU72_Discrete_MCRegisters), SMC_RAM_END);
smu_data         2206 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
smu_data         2213 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->power_tune_defaults =
smu_data         2217 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->power_tune_defaults = &tonga_power_tune_data_set_array[0];
smu_data         2224 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         2226 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table);
smu_data         2234 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
smu_data         2437 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags),
smu_data         2462 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         2482 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (0 == smu_data->smu7_data.fan_table_start) {
smu_data         2543 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 					smu_data->smu7_data.fan_table_start,
smu_data         2566 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         2582 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				smu_data->smu7_data.dpm_table_start +
smu_data         2677 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         2683 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.UvdBootLevel = 0;
smu_data         2685 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smc_state_table.UvdBootLevel =
smu_data         2687 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
smu_data         2694 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
smu_data         2705 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
smu_data         2711 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data =
smu_data         2718 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu_data->smc_state_table.VceBootLevel =
smu_data         2721 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
smu_data         2728 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
smu_data         2736 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
smu_data         2758 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
smu_data         2770 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smu7_data.dpm_table_start = tmp;
smu_data         2781 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smu7_data.soft_regs_start = tmp;
smu_data         2793 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smu7_data.mc_reg_table_start = tmp;
smu_data         2801 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smu7_data.fan_table_start = tmp;
smu_data         2811 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smu7_data.arb_table_start = tmp;
smu_data         3068 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
smu_data         3070 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_mc_reg_table *ni_table = &smu_data->mc_reg_table;
smu_data         3149 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)
smu_data         3153 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smu_data->smc_state_table.GraphicsLevel;
smu_data         3154 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu_data         3157 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
smu_data         3160 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smu_data->smc_state_table.MemoryLevel;
smu_data         3172 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
smu_data         3207 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
smu_data           84 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data;
smu_data           86 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data = kzalloc(sizeof(struct vegam_smumgr), GFP_KERNEL);
smu_data           87 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (smu_data == NULL)
smu_data           90 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	hwmgr->smu_backend = smu_data;
smu_data           93 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		kfree(smu_data);
smu_data          195 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data          199 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->protected_mode = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
smu_data          201 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smu7_data.security_hard_key = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(
smu_data          205 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (smu_data->protected_mode == 0)
smu_data          217 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			&(smu_data->smu7_data.soft_regs_start),
smu_data          227 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data          239 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smu7_data.dpm_table_start = tmp;
smu_data          250 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smu7_data.soft_regs_start = tmp;
smu_data          261 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smu7_data.mc_reg_table_start = tmp;
smu_data          269 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smu7_data.fan_table_start = tmp;
smu_data          279 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smu7_data.arb_table_start = tmp;
smu_data          333 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data          338 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->smc_state_table.UvdBootLevel = 0;
smu_data          340 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smc_state_table.UvdBootLevel =
smu_data          342 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable,
smu_data          349 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
smu_data          359 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
smu_data          365 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data          372 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smc_state_table.VceBootLevel =
smu_data          375 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smc_state_table.VceBootLevel = 0;
smu_data          377 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
smu_data          384 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
smu_data          391 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
smu_data          397 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data          408 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
smu_data          432 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data          439 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->power_tune_defaults =
smu_data          443 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->power_tune_defaults = &vegam_power_tune_data_set_array[0];
smu_data          571 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data =
smu_data          589 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->smc_state_table.LinkLevelCount =
smu_data          669 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data          698 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->range_table[i].trans_lower_frequency =
smu_data          700 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->range_table[i].trans_upper_frequency =
smu_data          719 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data          720 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
smu_data          749 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (clock > smu_data->range_table[i].trans_lower_frequency
smu_data          750 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		&& clock <= smu_data->range_table[i].trans_upper_frequency) {
smu_data          864 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data          871 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu_data          876 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			smu_data->smc_state_table.GraphicsLevel;
smu_data          883 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	vegam_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
smu_data          889 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				&(smu_data->smc_state_table.GraphicsLevel[i]));
smu_data          903 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
smu_data          905 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->smc_state_table.GraphicsDpmLevelCount =
smu_data         1034 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1038 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu_data         1043 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			smu_data->smc_state_table.MemoryLevel;
smu_data         1063 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->smc_state_table.MemoryDpmLevelCount =
smu_data         1289 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1309 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			smu_data->smu7_data.arb_table_start,
smu_data         1408 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1418 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			smu_data->smc_state_table.GraphicsBootLevel = level;
smu_data         1427 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			smu_data->smc_state_table.MemoryBootLevel = level;
smu_data         1444 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1446 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data         1447 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	SMU75_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
smu_data         1493 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data =
smu_data         1515 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
smu_data         1528 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
smu_data         1531 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->smc_state_table.LdoRefSel =
smu_data         1571 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1573 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	SMU75_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
smu_data         1678 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data =
smu_data         1712 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 					smu_data->smu7_data.soft_regs_start +
smu_data         1726 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				smu_data->smu7_data.soft_regs_start +
smu_data         1739 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1740 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data         1742 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
smu_data         1743 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
smu_data         1744 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
smu_data         1745 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
smu_data         1753 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1756 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data         1759 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->power_tune_table.TDC_VDDC_PkgLimit =
smu_data         1761 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
smu_data         1763 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
smu_data         1770 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1771 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data         1782 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
smu_data         1783 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->power_tune_table.LPMLTemperatureMin =
smu_data         1785 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->power_tune_table.LPMLTemperatureMax =
smu_data         1787 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
smu_data         1795 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1799 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
smu_data         1806 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1814 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
smu_data         1822 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1826 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->power_tune_table.GnbLPML[i] = 0;
smu_data         1833 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1836 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
smu_data         1837 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
smu_data         1843 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
smu_data         1845 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
smu_data         1853 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1902 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				(uint8_t *)&smu_data->power_tune_table,
smu_data         1927 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
smu_data         1931 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
smu_data         2111 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				smu_data->bif_sclk_table[i], &dividers);
smu_data         2140 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			smu_data->smu7_data.dpm_table_start +
smu_data         2221 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data =
smu_data         2236 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				smu_data->smu7_data.dpm_table_start +