smu7_data         311 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			&(priv->smu7_data.soft_regs_start), 0x40000);
smu7_data        1014 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu7_data        1230 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu7_data        1551 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				smu_data->smu7_data.arb_table_start,
smu7_data        1882 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
smu7_data        1891 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smu_data->smu7_data.arb_table_start,  tmp, SMC_RAM_END);
smu7_data        2110 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smu_data->smu7_data.dpm_table_start +
smu7_data        2151 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (smu_data->smu7_data.fan_table_start == 0) {
smu7_data        2217 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
smu7_data        2282 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				smu_data->smu7_data.dpm_table_start +
smu7_data        2379 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable,
smu7_data        2414 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
smu7_data        2461 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smu7_data.dpm_table_start = tmp;
smu7_data        2472 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smu7_data.soft_regs_start = tmp;
smu7_data        2483 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smu7_data.mc_reg_table_start = tmp;
smu7_data        2491 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smu7_data.fan_table_start = tmp;
smu7_data        2501 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smu_data->smu7_data.arb_table_start = tmp;
smu7_data        2558 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu7_data        2561 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
smu7_data          41 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h 	struct smu7_smumgr                   smu7_data;
smu7_data         253 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			&(priv->smu7_data.soft_regs_start), 0x40000);
smu7_data         964 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start +
smu7_data        1354 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel);
smu7_data        1637 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				smu_data->smu7_data.arb_table_start,
smu7_data        1794 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
smu7_data        1816 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
smu7_data        2057 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start +
smu7_data        2068 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			smu_data->smu7_data.ulv_setting_starts,
smu7_data        2087 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
smu7_data        2105 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (0 == smu7_data->fan_table_start) {
smu7_data        2157 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
smu7_data        2192 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				smu_data->smu7_data.dpm_table_start +
smu7_data        2280 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
smu7_data        2292 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu7_data->dpm_table_start = tmp;
smu7_data        2304 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu7_data->soft_regs_start = tmp;
smu7_data        2316 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu7_data->mc_reg_table_start = tmp;
smu7_data        2325 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu7_data->fan_table_start = tmp;
smu7_data        2336 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu7_data->arb_table_start = tmp;
smu7_data        2359 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		smu7_data->ulv_setting_starts = tmp;
smu7_data          61 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h 	struct smu7_smumgr smu7_data;
smu7_data         299 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
smu7_data         315 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 					&(smu_data->smu7_data.soft_regs_start), 0x40000);
smu7_data         987 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu7_data        1131 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu7_data        1385 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smu7_data.arb_table_start,
smu7_data        1629 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
smu7_data        1791 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
smu7_data        1800 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
smu7_data        2014 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smu_data->smu7_data.dpm_table_start +
smu7_data        2082 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (smu_data->smu7_data.fan_table_start == 0) {
smu7_data        2152 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
smu7_data        2188 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
smu7_data        2223 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
smu7_data        2293 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				smu_data->smu7_data.dpm_table_start +
smu7_data        2398 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smu7_data.dpm_table_start = tmp;
smu7_data        2409 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smu7_data.soft_regs_start = tmp;
smu7_data        2420 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smu7_data.mc_reg_table_start = tmp;
smu7_data        2428 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smu7_data.fan_table_start = tmp;
smu7_data        2438 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smu7_data.arb_table_start = tmp;
smu7_data        2471 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu7_data        2474 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
smu7_data          55 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h 	struct smu7_smumgr smu7_data;
smu7_data         220 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			&(priv->smu7_data.soft_regs_start), 0x40000);
smu7_data         694 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t level_array_address = smu_data->smu7_data.dpm_table_start +
smu7_data        1096 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				smu_data->smu7_data.dpm_table_start +
smu7_data        1512 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				smu_data->smu7_data.arb_table_start,
smu7_data        1813 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
smu7_data        1822 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
smu7_data        2173 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	address = smu_data->smu7_data.mc_reg_table_start +
smu7_data        2200 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
smu7_data        2437 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags),
smu7_data        2482 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (0 == smu_data->smu7_data.fan_table_start) {
smu7_data        2543 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 					smu_data->smu7_data.fan_table_start,
smu7_data        2582 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				smu_data->smu7_data.dpm_table_start +
smu7_data        2687 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
smu7_data        2721 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
smu7_data        2770 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smu7_data.dpm_table_start = tmp;
smu7_data        2781 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smu7_data.soft_regs_start = tmp;
smu7_data        2793 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smu7_data.mc_reg_table_start = tmp;
smu7_data        2801 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smu7_data.fan_table_start = tmp;
smu7_data        2811 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smu_data->smu7_data.arb_table_start = tmp;
smu7_data        3154 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu7_data        3157 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
smu7_data          65 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h 	struct smu7_smumgr                   smu7_data;
smu7_data         201 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smu7_data.security_hard_key = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(
smu7_data         217 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			&(smu_data->smu7_data.soft_regs_start),
smu7_data         239 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smu7_data.dpm_table_start = tmp;
smu7_data         250 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smu7_data.soft_regs_start = tmp;
smu7_data         261 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smu7_data.mc_reg_table_start = tmp;
smu7_data         269 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smu7_data.fan_table_start = tmp;
smu7_data         279 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->smu7_data.arb_table_start = tmp;
smu7_data         342 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable,
smu7_data         377 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
smu7_data         871 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu7_data        1038 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	uint32_t array = smu_data->smu7_data.dpm_table_start +
smu7_data        1309 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			smu_data->smu7_data.arb_table_start,
smu7_data        1712 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 					smu_data->smu7_data.soft_regs_start +
smu7_data        1726 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				smu_data->smu7_data.soft_regs_start +
smu7_data        2140 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			smu_data->smu7_data.dpm_table_start +
smu7_data        2236 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				smu_data->smu7_data.dpm_table_start +
smu7_data          64 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.h 	struct smu7_smumgr smu7_data;