smu10_ps          753 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps);
smu10_ps          755 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_ps->levels[index].engine_clock = 0;
smu10_ps          757 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_ps->levels[index].vddc_index = 0;
smu10_ps          758 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_ps->level = index + 1;
smu10_ps          761 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_ps->levels[index].ds_divider_index = 5;
smu10_ps          762 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_ps->levels[index].ss_divider_index = 5;
smu10_ps          782 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_power_state *smu10_ps;
smu10_ps          786 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_ps = cast_smu10_ps(&(ps->hardware));
smu10_ps          791 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
smu10_ps          792 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;