smu10_data         59 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data         66 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		if (clk_freq == smu10_data->dcf_actual_hard_min_freq)
smu10_data         69 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_data->dcf_actual_hard_min_freq = clk_freq;
smu10_data         75 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		if (clk_freq == smu10_data->f_actual_hard_min_freq)
smu10_data         77 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_data->f_actual_hard_min_freq = clk_freq;
smu10_data        108 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data        110 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->dce_slow_sclk_threshold = 30000;
smu10_data        111 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->thermal_auto_throttling_treshold = 0;
smu10_data        112 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->is_nb_dpm_enabled = 1;
smu10_data        113 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->dpm_flags = 1;
smu10_data        114 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->need_min_deep_sleep_dcefclk = true;
smu10_data        115 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->num_active_display = 0;
smu10_data        116 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->deep_sleep_dcefclk = 0;
smu10_data        172 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
smu10_data        174 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->sys_info.htc_hyst_lmt = 5;
smu10_data        175 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->sys_info.htc_tmp_lmt = 203;
smu10_data        177 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	if (smu10_data->thermal_auto_throttling_treshold == 0)
smu10_data        178 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		 smu10_data->thermal_auto_throttling_treshold = 203;
smu10_data        210 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data        212 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	if (smu10_data->need_min_deep_sleep_dcefclk &&
smu10_data        213 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_data->deep_sleep_dcefclk != clock) {
smu10_data        214 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_data->deep_sleep_dcefclk = clock;
smu10_data        217 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 					smu10_data->deep_sleep_dcefclk);
smu10_data        224 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data        226 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	if (smu10_data->dcf_actual_hard_min_freq &&
smu10_data        227 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_data->dcf_actual_hard_min_freq != clock) {
smu10_data        228 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_data->dcf_actual_hard_min_freq = clock;
smu10_data        231 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 					smu10_data->dcf_actual_hard_min_freq);
smu10_data        238 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data        240 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	if (smu10_data->f_actual_hard_min_freq &&
smu10_data        241 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_data->f_actual_hard_min_freq != clock) {
smu10_data        242 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_data->f_actual_hard_min_freq = clock;
smu10_data        245 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 					smu10_data->f_actual_hard_min_freq);
smu10_data        252 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data        254 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	if (smu10_data->num_active_display != count) {
smu10_data        255 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_data->num_active_display = count;
smu10_data        258 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 				smu10_data->num_active_display);
smu10_data        271 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data        274 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->vcn_power_gated = true;
smu10_data        275 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->isp_tileA_power_gated = true;
smu10_data        276 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->isp_tileB_power_gated = true;
smu10_data        294 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data        296 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->separation_time = 0;
smu10_data        297 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->cc6_disable = false;
smu10_data        298 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->pstate_disable = false;
smu10_data        299 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->cc6_setting_changed = false;
smu10_data        440 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data        441 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	DpmClocks_t  *table = &(smu10_data->clock_table);
smu10_data        442 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
smu10_data        453 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 						&smu10_data->clock_table.DcefClocks[0]);
smu10_data        456 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 						&smu10_data->clock_table.SocClocks[0]);
smu10_data        459 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 						&smu10_data->clock_table.FClocks[0]);
smu10_data        462 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 						&smu10_data->clock_table.MemClocks[0]);
smu10_data        484 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->gfx_min_freq_limit = result / 10 * 1000;
smu10_data        488 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_data->gfx_max_freq_limit = result / 10 * 1000;
smu10_data        542 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data        543 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
smu10_data        991 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data        992 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
smu10_data       1048 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data       1049 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
smu10_data       1119 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data       1142 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		*(uint32_t *)value =  smu10_data->vcn_power_gated ? 0 : 1;
smu10_data       1188 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
smu10_data       1196 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_data->vcn_power_gated = true;
smu10_data       1203 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_data->vcn_power_gated = false;