smu                32 arch/arm/mach-shmobile/smp-emev2.c 	void __iomem *smu;
smu                35 arch/arm/mach-shmobile/smp-emev2.c 	smu = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
smu                36 arch/arm/mach-shmobile/smp-emev2.c 	if (smu) {
smu                37 arch/arm/mach-shmobile/smp-emev2.c 		iowrite32(__pa(shmobile_boot_vector), smu + SMU_GENERAL_REG0);
smu                38 arch/arm/mach-shmobile/smp-emev2.c 		iounmap(smu);
smu               918 drivers/gpu/drm/amd/amdgpu/amdgpu.h 	struct smu_context		smu;
smu               660 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 		smu_switch_power_profile(&adev->smu,
smu               912 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c 		ret = smu_get_dpm_freq_range(&adev->smu, SMU_GFXCLK,
smu               929 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c 		ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK,
smu               953 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c 			ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate);
smu               302 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 		((adev)->smu.ppt_funcs->get_current_power_state(&((adev)->smu)))
smu               305 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 		((adev)->smu.ppt_funcs->set_power_state(&((adev)->smu)))
smu               109 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_read_sensor(&adev->smu, sensor, data, size);
smu               164 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		if (adev->smu.ppt_funcs->get_current_power_state)
smu               295 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		level = smu_get_performance_level(&adev->smu);
smu               366 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		current_level = smu_get_performance_level(&adev->smu);
smu               384 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_force_performance_level(&adev->smu, level);
smu               416 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_get_power_num_states(&adev->smu, &data);
smu               440 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 	struct smu_context *smu = &adev->smu;
smu               445 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		pm = smu_get_current_power_state(smu);
smu               446 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_get_power_num_states(smu, &data);
smu               540 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
smu               567 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
smu               694 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_od_edit_dpm_table(&adev->smu, type,
smu               731 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf);
smu               732 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size);
smu               733 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
smu               734 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
smu               781 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
smu               801 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		return smu_sys_get_pp_feature_mask(&adev->smu, buf);
smu               845 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		return smu_print_clk_levels(&adev->smu, SMU_SCLK, buf);
smu               906 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
smu               928 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		return smu_print_clk_levels(&adev->smu, SMU_MCLK, buf);
smu               953 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
smu               971 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		return smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf);
smu               993 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
smu              1011 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		return smu_print_clk_levels(&adev->smu, SMU_FCLK, buf);
smu              1033 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
smu              1051 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		return smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf);
smu              1073 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
smu              1091 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		return smu_print_clk_levels(&adev->smu, SMU_PCIE, buf);
smu              1113 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
smu              1132 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		value = smu_get_od_percentage(&(adev->smu), SMU_OD_SCLK);
smu              1157 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		value = smu_set_od_percentage(&(adev->smu), SMU_OD_SCLK, (uint32_t)value);
smu              1183 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		value = smu_get_od_percentage(&(adev->smu), SMU_OD_MCLK);
smu              1208 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		value = smu_set_od_percentage(&(adev->smu), SMU_OD_MCLK, (uint32_t)value);
smu              1253 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		return smu_get_power_profile_mode(&adev->smu, buf);
smu              1305 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
smu              1603 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		pwm_mode = smu_get_fan_control_mode(&adev->smu);
smu              1633 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		smu_set_fan_control_mode(&adev->smu, value);
smu              1672 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		pwm_mode = smu_get_fan_control_mode(&adev->smu);
smu              1687 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		err = smu_set_fan_speed_percent(&adev->smu, value);
smu              1713 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		err = smu_get_fan_speed_percent(&adev->smu, &speed);
smu              1741 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		err = smu_get_fan_speed_rpm(&adev->smu, &speed);
smu              1801 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		err = smu_get_fan_speed_rpm(&adev->smu, &rpm);
smu              1823 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		pwm_mode = smu_get_fan_control_mode(&adev->smu);
smu              1840 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		err = smu_set_fan_speed_rpm(&adev->smu, value);
smu              1860 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		pwm_mode = smu_get_fan_control_mode(&adev->smu);
smu              1898 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		smu_set_fan_control_mode(&adev->smu, pwm_mode);
smu              2014 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		smu_get_power_limit(&adev->smu, &limit, true);
smu              2032 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		smu_get_power_limit(&adev->smu, &limit, false);
smu              2059 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		err = smu_set_power_limit(&adev->smu, value);
smu              2666 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 	    ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
smu              2693 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 	    ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
smu              2879 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 	if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
smu              2975 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 	if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
smu              3009 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
smu              3010 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		smu_handle_task(&adev->smu,
smu               286 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 		ret = smu_set_xgmi_pstate(&adev->smu, pstate);
smu              3790 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		r = smu_load_microcode(&adev->smu);
smu              3794 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		r = smu_check_fw_status(&adev->smu);
smu              4583 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		smu_set_gfx_cgpg(&adev->smu, enable);
smu              4860 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			smu_set_gfx_cgpg(&adev->smu, enable);
smu               297 drivers/gpu/drm/amd/amdgpu/nv.c 	struct smu_context *smu = &adev->smu;
smu               299 drivers/gpu/drm/amd/amdgpu/nv.c 	if (smu_baco_is_support(smu))
smu               317 drivers/gpu/drm/amd/amdgpu/nv.c 	struct smu_context *smu = &adev->smu;
smu               322 drivers/gpu/drm/amd/amdgpu/nv.c 		ret = smu_baco_reset(smu);
smu                43 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct smu_context *smu = &adev->smu;
smu               110 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 			smu_display_configuration_change(smu,
smu               349 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	} else if (adev->smu.funcs && adev->smu.funcs->get_clock_by_type) {
smu               350 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		if (smu_get_clock_by_type(&adev->smu,
smu               369 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	} else if (adev->smu.funcs && adev->smu.funcs->get_max_high_clocks) {
smu               370 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		if (smu_get_max_high_clocks(&adev->smu, &validation_clks)) {
smu               434 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	} else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type_with_latency) {
smu               435 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		if (smu_get_clock_by_type_with_latency(&adev->smu,
smu               464 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	} else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type_with_voltage) {
smu               465 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		if (smu_get_clock_by_type_with_voltage(&adev->smu,
smu               510 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	else if (adev->smu.funcs &&
smu               511 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		 adev->smu.funcs->display_clock_voltage_request)
smu               512 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		ret = smu_display_clock_voltage_request(&adev->smu,
smu               531 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	else if (adev->smu.funcs)
smu               532 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		ret = smu_get_current_clocks(&adev->smu, &pp_clk_info);
smu               593 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	else if (adev->smu.funcs &&
smu               594 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		 adev->smu.funcs->set_watermarks_for_clock_ranges)
smu               595 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		smu_set_watermarks_for_clock_ranges(&adev->smu,
smu               608 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	else if (adev->smu.funcs)
smu               609 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		smu_notify_smu_enable_pwe(&adev->smu);
smu               669 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct smu_context *smu = &adev->smu;
smu               712 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (!smu->funcs)
smu               718 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (smu_set_watermarks_for_clock_ranges(&adev->smu,
smu               729 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct smu_context *smu = &adev->smu;
smu               731 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (!smu->funcs)
smu               735 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (smu_set_azalia_d3_pme(smu))
smu               745 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct smu_context *smu = &adev->smu;
smu               747 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (!smu->funcs)
smu               751 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (smu_set_display_count(smu, count))
smu               761 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct smu_context *smu = &adev->smu;
smu               763 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (!smu->funcs)
smu               767 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (smu_set_deep_sleep_dcefclk(smu, mhz))
smu               778 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct smu_context *smu = &adev->smu;
smu               781 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (!smu->funcs)
smu               790 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (smu_display_clock_voltage_request(smu, &clock_req))
smu               800 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct smu_context *smu = &adev->smu;
smu               803 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (!smu->funcs)
smu               812 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (smu_display_clock_voltage_request(smu, &clock_req))
smu               823 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct smu_context *smu = &adev->smu;
smu               825 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (smu_display_disable_memory_clock_switch(smu, !pstate_handshake_supported))
smu               836 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct smu_context *smu = &adev->smu;
smu               839 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (!smu->funcs)
smu               860 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (smu_display_clock_voltage_request(smu, &clock_req))
smu               871 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct smu_context *smu = &adev->smu;
smu               873 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (!smu->funcs)
smu               876 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (!smu->funcs->get_max_sustainable_clocks_by_dc)
smu               879 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (!smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks))
smu               890 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct smu_context *smu = &adev->smu;
smu               892 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (!smu->ppt_funcs)
smu               895 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (!smu->ppt_funcs->get_uclk_dpm_states)
smu               898 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (!smu->ppt_funcs->get_uclk_dpm_states(smu,
smu                40 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
smu                53 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
smu                60 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
smu                70 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
smu                78 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		feature_index = smu_feature_get_index(smu, i);
smu                88 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			       smu_get_feature_name(smu, sort_feature[i]),
smu                90 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			       !!smu_feature_is_enabled(smu, sort_feature[i]) ?
smu                98 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
smu               106 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
smu               116 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
smu               121 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
smu               129 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
smu               137 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
smu               141 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_read_smc_arg(smu, if_version);
smu               147 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
smu               151 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_read_smc_arg(smu, smu_version);
smu               159 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
smu               168 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu_clk_dpm_is_enabled(smu, clk_type))
smu               171 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	clk_id = smu_clk_get_index(smu, clk_type);
smu               177 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
smu               185 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
smu               195 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
smu               204 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu_clk_dpm_is_enabled(smu, clk_type))
smu               207 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	clk_id = smu_clk_get_index(smu, clk_type);
smu               213 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
smu               221 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
smu               231 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
smu               240 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
smu               244 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			clock_limit = smu->smu_table.boot_values.uclk;
smu               248 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			clock_limit = smu->smu_table.boot_values.gfxclk;
smu               251 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			clock_limit = smu->smu_table.boot_values.socclk;
smu               270 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
smu               274 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
smu               283 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu_clk_dpm_is_enabled(smu, clk_type))
smu               286 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	clk_id = smu_clk_get_index(smu, clk_type);
smu               292 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
smu               297 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_read_smc_arg(smu, &param);
smu               308 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
smu               311 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
smu               314 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
smu               334 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if(!smu_feature_is_enabled(smu, feature_id)) {
smu               342 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
smu               349 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_dpm_set_uvd_enable(smu, gate);
smu               352 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_dpm_set_vce_enable(smu, gate);
smu               355 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_gfx_off_control(smu, gate);
smu               358 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_powergate_sdma(smu, gate);
smu               367 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
smu               373 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_power_num_states(struct smu_context *smu,
smu               387 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
smu               390 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_power_context *smu_power = &smu->smu_power;
smu               399 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		*((uint32_t *)data) = smu->pstate_sclk;
smu               403 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		*((uint32_t *)data) = smu->pstate_mclk;
smu               407 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
smu               411 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		*(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
smu               415 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		*(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
smu               433 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
smu               436 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               437 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct amdgpu_device *adev = smu->adev;
smu               440 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	int table_id = smu_table_get_index(smu, table_index);
smu               450 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
smu               454 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
smu               458 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_send_smc_msg_with_param(smu, drv2smu ?
smu               495 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_sys_get_pp_table(struct smu_context *smu, void **table)
smu               497 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               510 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
smu               512 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               516 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu->pm_enabled)
smu               523 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_lock(&smu->mutex);
smu               534 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_unlock(&smu->mutex);
smu               536 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_reset(smu);
smu               543 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_unlock(&smu->mutex);
smu               547 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_feature_init_dpm(struct smu_context *smu)
smu               549 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_feature *feature = &smu->smu_feature;
smu               553 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu->pm_enabled)
smu               559 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
smu               572 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled)
smu               577 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu->pm_enabled)
smu               584 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
smu               588 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
smu               594 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
smu               598 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
smu               608 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
smu               610 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct amdgpu_device *adev = smu->adev;
smu               611 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_feature *feature = &smu->smu_feature;
smu               618 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	feature_id = smu_feature_get_index(smu, mask);
smu               631 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
smu               634 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_feature *feature = &smu->smu_feature;
smu               639 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	feature_id = smu_feature_get_index(smu, mask);
smu               648 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_feature_update_enable_state(smu, feature_mask, enable);
smu               663 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
smu               665 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_feature *feature = &smu->smu_feature;
smu               669 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	feature_id = smu_feature_get_index(smu, mask);
smu               682 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_feature_set_supported(struct smu_context *smu,
smu               686 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_feature *feature = &smu->smu_feature;
smu               690 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	feature_id = smu_feature_get_index(smu, mask);
smu               708 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_context *smu = &adev->smu;
smu               717 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			smu->od_enabled = true;
smu               718 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu_v11_0_set_smu_funcs(smu);
smu               722 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			smu->od_enabled = true;
smu               723 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu_v12_0_set_smu_funcs(smu);
smu               735 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_context *smu = &adev->smu;
smu               737 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->adev = adev;
smu               738 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->pm_enabled = !!amdgpu_dpm;
smu               739 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_init(&smu->mutex);
smu               747 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_context *smu = &adev->smu;
smu               749 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu->pm_enabled)
smu               752 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_lock(&smu->mutex);
smu               753 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu_handle_task(&adev->smu,
smu               754 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			smu->smu_dpm.dpm_level,
smu               756 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_unlock(&smu->mutex);
smu               761 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
smu               765 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct amdgpu_device *adev = smu->adev;
smu               777 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c static int smu_initialize_pptable(struct smu_context *smu)
smu               783 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c static int smu_smc_table_sw_init(struct smu_context *smu)
smu               787 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_initialize_pptable(smu);
smu               797 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_init_smc_tables(smu);
smu               807 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_init_power(smu);
smu               816 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c static int smu_smc_table_sw_fini(struct smu_context *smu)
smu               820 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_fini_smc_tables(smu);
smu               832 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_context *smu = &adev->smu;
smu               835 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->pool_size = adev->pm.smu_prv_buffer_size;
smu               836 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->smu_feature.feature_num = SMU_FEATURE_MAX;
smu               837 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_init(&smu->smu_feature.mutex);
smu               838 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
smu               839 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
smu               840 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
smu               842 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_init(&smu->smu_baco.mutex);
smu               843 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->smu_baco.state = SMU_BACO_STATE_EXIT;
smu               844 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->smu_baco.platform_support = false;
smu               846 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_init(&smu->sensor_lock);
smu               847 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_init(&smu->metrics_lock);
smu               849 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->watermarks_bitmap = 0;
smu               850 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
smu               851 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
smu               853 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
smu               854 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
smu               855 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
smu               856 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
smu               857 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
smu               858 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
smu               859 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
smu               860 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
smu               862 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
smu               863 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
smu               864 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
smu               865 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
smu               866 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
smu               867 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
smu               868 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
smu               869 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->display_config = &adev->pm.pm_display_cfg;
smu               871 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
smu               872 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
smu               873 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_init_microcode(smu);
smu               879 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_smc_table_sw_init(smu);
smu               885 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_register_irq_handler(smu);
smu               897 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_context *smu = &adev->smu;
smu               900 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	kfree(smu->irq_source);
smu               901 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->irq_source = NULL;
smu               903 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_smc_table_sw_fini(smu);
smu               909 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_fini_power(smu);
smu               918 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c static int smu_init_fb_allocations(struct smu_context *smu)
smu               920 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct amdgpu_device *adev = smu->adev;
smu               921 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               957 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c static int smu_fini_fb_allocations(struct smu_context *smu)
smu               959 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               978 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c static int smu_override_pcie_parameters(struct smu_context *smu)
smu               980 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct amdgpu_device *adev = smu->adev;
smu              1014 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_send_smc_msg_with_param(smu,
smu              1022 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c static int smu_smc_table_hw_init(struct smu_context *smu,
smu              1025 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct amdgpu_device *adev = smu->adev;
smu              1028 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (smu_is_dpm_running(smu) && adev->in_suspend) {
smu              1034 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_init_display_count(smu, 0);
smu              1041 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_get_vbios_bootup_values(smu);
smu              1045 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_setup_pptable(smu);
smu              1049 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_get_clk_info_from_vbios(smu);
smu              1057 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_check_pptable(smu);
smu              1064 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_init_fb_allocations(smu);
smu              1073 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_parse_pptable(smu);
smu              1081 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_check_fw_version(smu);
smu              1092 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_write_pptable(smu);
smu              1097 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_run_afll_btc(smu);
smu              1101 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_feature_set_allowed_mask(smu);
smu              1105 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_system_features_control(smu, true);
smu              1110 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_override_pcie_parameters(smu);
smu              1114 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_notify_display_change(smu);
smu              1122 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_set_min_dcef_deep_sleep(smu);
smu              1133 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_populate_smc_tables(smu);
smu              1137 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_init_max_sustainable_clocks(smu);
smu              1142 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_set_default_od_settings(smu, initialize);
smu              1147 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_populate_umd_state_clk(smu);
smu              1151 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_get_power_limit(smu, &smu->default_power_limit, true);
smu              1159 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_set_tool_table_location(smu);
smu              1161 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu_is_dpm_running(smu))
smu              1177 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c static int smu_alloc_memory_pool(struct smu_context *smu)
smu              1179 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct amdgpu_device *adev = smu->adev;
smu              1180 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu              1182 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	uint64_t pool_size = smu->pool_size;
smu              1212 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c static int smu_free_memory_pool(struct smu_context *smu)
smu              1214 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu              1234 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_context *smu = &adev->smu;
smu              1238 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			ret = smu_load_microcode(smu);
smu              1244 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_check_fw_status(smu);
smu              1251 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu_powergate_sdma(&adev->smu, false);
smu              1252 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu_powergate_vcn(&adev->smu, false);
smu              1255 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu->pm_enabled)
smu              1258 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_feature_init_dpm(smu);
smu              1262 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_smc_table_hw_init(smu, true);
smu              1266 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_alloc_memory_pool(smu);
smu              1274 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_notify_memory_pool_location(smu);
smu              1278 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_start_thermal_control(smu);
smu              1282 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu->pm_enabled)
smu              1298 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_context *smu = &adev->smu;
smu              1299 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              1303 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu_powergate_sdma(&adev->smu, true);
smu              1304 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu_powergate_vcn(&adev->smu, true);
smu              1316 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_fini_fb_allocations(smu);
smu              1320 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_free_memory_pool(smu);
smu              1327 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_reset(struct smu_context *smu)
smu              1329 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct amdgpu_device *adev = smu->adev;
smu              1347 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_context *smu = &adev->smu;
smu              1351 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
smu              1353 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_system_features_control(smu, false);
smu              1358 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
smu              1365 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
smu              1378 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_context *smu = &adev->smu;
smu              1382 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_lock(&smu->mutex);
smu              1384 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_smc_table_hw_init(smu, false);
smu              1388 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_start_thermal_control(smu);
smu              1392 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_unlock(&smu->mutex);
smu              1398 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_unlock(&smu->mutex);
smu              1402 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_display_configuration_change(struct smu_context *smu,
smu              1408 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
smu              1414 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_lock(&smu->mutex);
smu              1416 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu_set_deep_sleep_dcefclk(smu,
smu              1424 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu_set_active_display_count(smu, num_of_active_display);
smu              1426 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
smu              1431 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_unlock(&smu->mutex);
smu              1436 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c static int smu_get_clock_info(struct smu_context *smu,
smu              1446 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
smu              1454 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_get_perf_level(smu, designation, &level);
smu              1465 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_current_clocks(struct smu_context *smu,
smu              1472 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!is_support_sw_smu(smu->adev))
smu              1475 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_lock(&smu->mutex);
smu              1477 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu_get_dal_power_level(smu, &simple_clocks);
smu              1479 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (smu->support_power_containment)
smu              1480 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_get_clock_info(smu, &hw_clocks,
smu              1483 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
smu              1504 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
smu              1510 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_unlock(&smu->mutex);
smu              1534 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_context *smu = (struct smu_context*)(handle);
smu              1535 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
smu              1536 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu->pm_enabled || !smu_dpm_ctx->dpm_context)
smu              1544 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			amdgpu_device_ip_set_powergating_state(smu->adev,
smu              1547 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			amdgpu_device_ip_set_clockgating_state(smu->adev,
smu              1557 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			amdgpu_device_ip_set_clockgating_state(smu->adev,
smu              1560 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			amdgpu_device_ip_set_powergating_state(smu->adev,
smu              1569 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c static int smu_default_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
smu              1576 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_force_dpm_limit_value(smu, true);
smu              1579 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_force_dpm_limit_value(smu, false);
smu              1583 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_unforce_dpm_levels(smu);
smu              1588 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_get_profiling_clk_mask(smu, level,
smu              1594 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
smu              1595 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
smu              1596 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
smu              1606 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_adjust_power_state_dynamic(struct smu_context *smu,
smu              1613 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
smu              1615 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu->pm_enabled)
smu              1619 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_display_config_changed(smu);
smu              1626 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_apply_clocks_adjust_rules(smu);
smu              1633 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_notify_smc_dispaly_config(smu);
smu              1641 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_asic_set_performance_level(smu, level);
smu              1643 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			ret = smu_default_set_performance_level(smu, level);
smu              1655 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		index = fls(smu->workload_mask);
smu              1657 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		workload = smu->workload_setting[index];
smu              1659 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		if (smu->power_profile_mode != workload)
smu              1660 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			smu_set_power_profile_mode(smu, &workload, 0);
smu              1666 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_handle_task(struct smu_context *smu,
smu              1674 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_pre_display_config_changed(smu);
smu              1677 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_set_cpu_power_state(smu);
smu              1680 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_adjust_power_state_dynamic(smu, level, false);
smu              1684 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		ret = smu_adjust_power_state_dynamic(smu, level, true);
smu              1693 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_switch_power_profile(struct smu_context *smu,
smu              1697 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
smu              1701 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!smu->pm_enabled)
smu              1707 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_lock(&smu->mutex);
smu              1710 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu->workload_mask &= ~(1 << smu->workload_prority[type]);
smu              1711 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		index = fls(smu->workload_mask);
smu              1713 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		workload = smu->workload_setting[index];
smu              1715 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu->workload_mask |= (1 << smu->workload_prority[type]);
smu              1716 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		index = fls(smu->workload_mask);
smu              1718 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		workload = smu->workload_setting[index];
smu              1722 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu_set_power_profile_mode(smu, &workload, 0);
smu              1724 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_unlock(&smu->mutex);
smu              1729 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
smu              1731 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
smu              1737 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_lock(&(smu->mutex));
smu              1739 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_unlock(&(smu->mutex));
smu              1744 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
smu              1746 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
smu              1752 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_enable_umd_pstate(smu, &level);
smu              1756 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_handle_task(smu, level,
smu              1762 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_set_display_count(struct smu_context *smu, uint32_t count)
smu              1766 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_lock(&smu->mutex);
smu              1767 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_init_display_count(smu, count);
smu              1768 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	mutex_unlock(&smu->mutex);
smu               268 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
smu               284 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
smu               286 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               305 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_allocate_dpm_context(struct smu_context *smu)
smu               307 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu               341 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c arcturus_get_allowed_feature_mask(struct smu_context *smu,
smu               354 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c arcturus_set_single_dpm_table(struct smu_context *smu,
smu               361 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = smu_send_smc_msg_with_param(smu,
smu               369 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	smu_read_smc_arg(smu, &num_of_levels);
smu               377 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = smu_send_smc_msg_with_param(smu,
smu               384 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		smu_read_smc_arg(smu, &clk);
smu               403 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_set_default_dpm_table(struct smu_context *smu)
smu               407 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu               415 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
smu               416 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
smu               424 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
smu               430 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
smu               431 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
smu               439 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
smu               445 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
smu               446 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
smu               454 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
smu               460 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
smu               461 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
smu               469 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
smu               479 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_check_powerplay_table(struct smu_context *smu)
smu               484 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_store_powerplay_table(struct smu_context *smu)
smu               487 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu               503 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_append_powerplay_table(struct smu_context *smu)
smu               505 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu               513 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
smu               531 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_run_btc_afll(struct smu_context *smu)
smu               533 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
smu               536 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_populate_umd_state_clk(struct smu_context *smu)
smu               538 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu               547 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	smu->pstate_sclk = gfx_table->dpm_levels[0].value;
smu               548 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	smu->pstate_mclk = mem_table->dpm_levels[0].value;
smu               552 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
smu               553 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
smu               556 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	smu->pstate_sclk = smu->pstate_sclk * 100;
smu               557 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	smu->pstate_mclk = smu->pstate_mclk * 100;
smu               562 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_clk_table(struct smu_context *smu,
smu               586 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_print_clk_levels(struct smu_context *smu,
smu               593 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu               600 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
smu               607 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
smu               622 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
smu               629 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
smu               644 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
smu               651 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
smu               666 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
smu               673 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
smu               694 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
smu               699 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 			smu->smu_dpm.dpm_context;
smu               703 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
smu               708 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = smu_send_smc_msg_with_param(smu,
smu               718 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
smu               723 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = smu_send_smc_msg_with_param(smu,
smu               733 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
smu               738 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = smu_send_smc_msg_with_param(smu,
smu               751 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_force_clk_levels(struct smu_context *smu,
smu               759 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	mutex_lock(&(smu->mutex));
smu               764 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	dpm_table = smu->smu_dpm.dpm_context;
smu               782 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
smu               788 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
smu               809 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
smu               815 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
smu               836 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
smu               842 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
smu               863 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
smu               869 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
smu               879 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	mutex_unlock(&(smu->mutex));
smu               883 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
smu               886 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	PPTable_t *pptable = smu->smu_table.driver_pptable;
smu               907 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_metrics_table(struct smu_context *smu,
smu               910 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	struct smu_table_context *smu_table= &smu->smu_table;
smu               913 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	mutex_lock(&smu->metrics_lock);
smu               916 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
smu               920 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 			mutex_unlock(&smu->metrics_lock);
smu               927 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	mutex_unlock(&smu->metrics_lock);
smu               932 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_current_activity_percent(struct smu_context *smu,
smu               942 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = arcturus_get_metrics_table(smu, &metrics);
smu               961 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
smu               969 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = arcturus_get_metrics_table(smu, &metrics);
smu               978 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_thermal_get_temperature(struct smu_context *smu,
smu               988 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = arcturus_get_metrics_table(smu, &metrics);
smu              1013 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_read_sensor(struct smu_context *smu,
smu              1017 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              1024 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	mutex_lock(&smu->sensor_lock);
smu              1032 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_get_current_activity_percent(smu,
smu              1038 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
smu              1044 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = arcturus_thermal_get_temperature(smu, sensor,
smu              1049 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		ret = smu_smc_read_sensor(smu, sensor, data, size);
smu              1051 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	mutex_unlock(&smu->sensor_lock);
smu              1056 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
smu              1065 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = arcturus_get_metrics_table(smu, &metrics);
smu              1074 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_fan_speed_percent(struct smu_context *smu,
smu              1077 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	PPTable_t *pptable = smu->smu_table.driver_pptable;
smu              1084 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
smu              1094 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
smu              1104 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	clk_id = smu_clk_get_index(smu, clk_type);
smu              1108 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = arcturus_get_metrics_table(smu, &metrics);
smu              1120 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
smu              1126 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
smu              1132 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
smu              1188 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
smu              1191 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
smu              1225 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
smu              1232 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
smu              1242 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_unforce_dpm_levels(struct smu_context *smu)
smu              1245 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
smu              1273 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
smu              1279 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
smu              1289 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c arcturus_get_profiling_clk_mask(struct smu_context *smu,
smu              1296 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
smu              1301 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	if (!smu->smu_dpm.dpm_context)
smu              1333 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_power_limit(struct smu_context *smu,
smu              1337 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	PPTable_t *pptable = smu->smu_table.driver_pptable;
smu              1342 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	if (!smu->default_power_limit ||
smu              1343 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	    !smu->power_limit) {
smu              1344 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
smu              1345 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 			power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
smu              1349 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
smu              1355 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 			smu_read_smc_arg(smu, &asic_default_power_limit);
smu              1366 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		if (smu->od_enabled) {
smu              1367 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 			asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
smu              1371 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		smu->default_power_limit = asic_default_power_limit;
smu              1372 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		smu->power_limit = asic_default_power_limit;
smu              1376 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		*limit = smu->default_power_limit;
smu              1378 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		*limit = smu->power_limit;
smu              1383 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_power_profile_mode(struct smu_context *smu,
smu              1399 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	if (!smu->pm_enabled || !buf)
smu              1410 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		workload_type = smu_workload_get_type(smu, i);
smu              1415 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 			i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
smu              1421 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_set_power_profile_mode(struct smu_context *smu,
smu              1429 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	if (!smu->pm_enabled)
smu              1441 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	workload_type = smu_workload_get_type(smu, profile_mode);
smu              1447 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = smu_send_smc_msg_with_param(smu,
smu              1455 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	smu->power_profile_mode = profile_mode;
smu              1460 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static void arcturus_dump_pptable(struct smu_context *smu)
smu              1462 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              1891 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static bool arcturus_is_dpm_running(struct smu_context *smu)
smu              1896 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
smu              1942 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c void arcturus_set_ppt_funcs(struct smu_context *smu)
smu              1944 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu              1946 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	smu->ppt_funcs = &arcturus_ppt_funcs;
smu                70 drivers/gpu/drm/amd/powerplay/arcturus_ppt.h extern void arcturus_set_ppt_funcs(struct smu_context *smu);
smu               392 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*alloc_dpm_context)(struct smu_context *smu);
smu               393 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*store_powerplay_table)(struct smu_context *smu);
smu               394 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*check_powerplay_table)(struct smu_context *smu);
smu               395 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*append_powerplay_table)(struct smu_context *smu);
smu               396 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
smu               397 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_smu_clk_index)(struct smu_context *smu, uint32_t index);
smu               398 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index);
smu               399 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_smu_table_index)(struct smu_context *smu, uint32_t index);
smu               400 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_smu_power_index)(struct smu_context *smu, uint32_t index);
smu               401 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_workload_type)(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile);
smu               402 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*run_afll_btc)(struct smu_context *smu);
smu               403 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
smu               404 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
smu               405 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_default_dpm_table)(struct smu_context *smu);
smu               406 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_power_state)(struct smu_context *smu);
smu               407 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*populate_umd_state_clk)(struct smu_context *smu);
smu               408 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
smu               409 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
smu               410 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_default_od8_settings)(struct smu_context *smu);
smu               411 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type);
smu               412 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_od_percentage)(struct smu_context *smu,
smu               415 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*od_edit_dpm_table)(struct smu_context *smu,
smu               418 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_clock_by_type_with_latency)(struct smu_context *smu,
smu               423 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
smu               428 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
smu               429 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
smu               430 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
smu               431 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
smu               432 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
smu               434 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*pre_display_config_changed)(struct smu_context *smu);
smu               435 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*display_config_changed)(struct smu_context *smu);
smu               436 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*apply_clocks_adjust_rules)(struct smu_context *smu);
smu               437 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*notify_smc_dispaly_config)(struct smu_context *smu);
smu               438 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
smu               439 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*unforce_dpm_levels)(struct smu_context *smu);
smu               440 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_profiling_clk_mask)(struct smu_context *smu,
smu               445 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_cpu_power_state)(struct smu_context *smu);
smu               446 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	bool (*is_dpm_running)(struct smu_context *smu);
smu               447 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
smu               448 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_thermal_fan_table)(struct smu_context *smu);
smu               449 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
smu               450 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
smu               451 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
smu               453 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_current_clk_freq_by_table)(struct smu_context *smu,
smu               456 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
smu               457 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
smu               458 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
smu               459 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
smu               460 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
smu               461 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	void (*dump_pptable)(struct smu_context *smu);
smu               462 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default);
smu               463 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_dpm_uclk_limited)(struct smu_context *smu, uint32_t *clock, bool max);
smu               468 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*init_microcode)(struct smu_context *smu);
smu               469 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*init_smc_tables)(struct smu_context *smu);
smu               470 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*fini_smc_tables)(struct smu_context *smu);
smu               471 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*init_power)(struct smu_context *smu);
smu               472 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*fini_power)(struct smu_context *smu);
smu               473 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*load_microcode)(struct smu_context *smu);
smu               474 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*check_fw_status)(struct smu_context *smu);
smu               475 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*setup_pptable)(struct smu_context *smu);
smu               476 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_vbios_bootup_values)(struct smu_context *smu);
smu               477 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_clk_info_from_vbios)(struct smu_context *smu);
smu               478 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*check_pptable)(struct smu_context *smu);
smu               479 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*parse_pptable)(struct smu_context *smu);
smu               480 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*populate_smc_tables)(struct smu_context *smu);
smu               481 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*check_fw_version)(struct smu_context *smu);
smu               482 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*powergate_sdma)(struct smu_context *smu, bool gate);
smu               483 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*powergate_vcn)(struct smu_context *smu, bool gate);
smu               484 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
smu               485 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*write_pptable)(struct smu_context *smu);
smu               486 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
smu               487 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_tool_table_location)(struct smu_context *smu);
smu               488 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*notify_memory_pool_location)(struct smu_context *smu);
smu               489 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*write_watermarks_table)(struct smu_context *smu);
smu               490 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
smu               491 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*system_features_control)(struct smu_context *smu, bool en);
smu               492 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
smu               493 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
smu               494 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
smu               495 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*init_display_count)(struct smu_context *smu, uint32_t count);
smu               496 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_allowed_mask)(struct smu_context *smu);
smu               497 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
smu               498 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*notify_display_change)(struct smu_context *smu);
smu               499 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_power_limit)(struct smu_context *smu, uint32_t n);
smu               500 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value);
smu               501 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*init_max_sustainable_clocks)(struct smu_context *smu);
smu               502 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*start_thermal_control)(struct smu_context *smu);
smu               503 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
smu               505 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
smu               506 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
smu               507 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
smu               510 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_clock_by_type)(struct smu_context *smu,
smu               513 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_max_high_clocks)(struct smu_context *smu,
smu               515 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*display_clock_voltage_request)(struct smu_context *smu, struct
smu               518 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_dal_power_level)(struct smu_context *smu,
smu               520 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_perf_level)(struct smu_context *smu,
smu               523 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
smu               525 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*notify_smu_enable_pwe)(struct smu_context *smu);
smu               526 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
smu               529 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	uint32_t (*get_fan_control_mode)(struct smu_context *smu);
smu               530 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
smu               531 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
smu               532 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
smu               533 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
smu               534 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*gfx_off_control)(struct smu_context *smu, bool enable);
smu               535 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*register_irq_handler)(struct smu_context *smu);
smu               536 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_azalia_d3_pme)(struct smu_context *smu);
smu               537 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
smu               538 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	bool (*baco_is_support)(struct smu_context *smu);
smu               539 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
smu               540 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
smu               541 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*baco_reset)(struct smu_context *smu);
smu               542 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
smu               545 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_init_microcode(smu) \
smu               546 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
smu               547 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_init_smc_tables(smu) \
smu               548 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
smu               549 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_fini_smc_tables(smu) \
smu               550 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
smu               551 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_init_power(smu) \
smu               552 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
smu               553 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_fini_power(smu) \
smu               554 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
smu               555 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_load_microcode(smu) \
smu               556 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
smu               557 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_check_fw_status(smu) \
smu               558 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
smu               559 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_setup_pptable(smu) \
smu               560 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
smu               561 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_powergate_sdma(smu, gate) \
smu               562 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
smu               563 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_powergate_vcn(smu, gate) \
smu               564 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
smu               565 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_gfx_cgpg(smu, enabled) \
smu               566 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu), (enabled)) : 0)
smu               567 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_vbios_bootup_values(smu) \
smu               568 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
smu               569 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_clk_info_from_vbios(smu) \
smu               570 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
smu               571 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_check_pptable(smu) \
smu               572 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
smu               573 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_parse_pptable(smu) \
smu               574 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
smu               575 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_populate_smc_tables(smu) \
smu               576 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
smu               577 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_check_fw_version(smu) \
smu               578 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
smu               579 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_write_pptable(smu) \
smu               580 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
smu               581 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_min_dcef_deep_sleep(smu) \
smu               582 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
smu               583 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_tool_table_location(smu) \
smu               584 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
smu               585 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_notify_memory_pool_location(smu) \
smu               586 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
smu               587 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_gfx_off_control(smu, enable) \
smu               588 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
smu               590 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_write_watermarks_table(smu) \
smu               591 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
smu               592 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_last_dcef_min_deep_sleep_clk(smu) \
smu               593 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
smu               594 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_system_features_control(smu, en) \
smu               595 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
smu               596 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_init_max_sustainable_clocks(smu) \
smu               597 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
smu               598 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_default_od_settings(smu, initialize) \
smu               599 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
smu               600 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_fan_speed_rpm(smu, speed) \
smu               601 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
smu               602 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_send_smc_msg(smu, msg) \
smu               603 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
smu               604 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_send_smc_msg_with_param(smu, msg, param) \
smu               605 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
smu               606 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_read_smc_arg(smu, arg) \
smu               607 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
smu               608 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_alloc_dpm_context(smu) \
smu               609 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
smu               610 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_init_display_count(smu, count) \
smu               611 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
smu               612 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_feature_set_allowed_mask(smu) \
smu               613 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
smu               614 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_feature_get_enabled_mask(smu, mask, num) \
smu               615 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
smu               616 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_is_dpm_running(smu) \
smu               617 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
smu               618 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_notify_display_change(smu) \
smu               619 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
smu               620 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_store_powerplay_table(smu) \
smu               621 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
smu               622 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_check_powerplay_table(smu) \
smu               623 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
smu               624 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_append_powerplay_table(smu) \
smu               625 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
smu               626 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_default_dpm_table(smu) \
smu               627 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
smu               628 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_populate_umd_state_clk(smu) \
smu               629 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
smu               630 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_default_od8_settings(smu) \
smu               631 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
smu               632 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_power_limit(smu, limit, def) \
smu               633 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit((smu), (limit), (def)) : 0)
smu               634 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_power_limit(smu, limit) \
smu               635 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
smu               636 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_current_clk_freq(smu, clk_id, value) \
smu               637 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
smu               638 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_print_clk_levels(smu, clk_type, buf) \
smu               639 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
smu               640 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_force_clk_levels(smu, clk_type, level) \
smu               641 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (clk_type), (level)) : 0)
smu               642 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_od_percentage(smu, type) \
smu               643 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
smu               644 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_od_percentage(smu, type, value) \
smu               645 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
smu               646 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_od_edit_dpm_table(smu, type, input, size) \
smu               647 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
smu               648 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_tables_init(smu, tab) \
smu               649 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
smu               650 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_thermal_fan_table(smu) \
smu               651 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
smu               652 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_start_thermal_control(smu) \
smu               653 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
smu               654 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_read_sensor(smu, sensor, data, size) \
smu               655 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
smu               656 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_smc_read_sensor(smu, sensor, data, size) \
smu               657 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
smu               658 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_power_profile_mode(smu, buf) \
smu               659 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
smu               660 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_power_profile_mode(smu, param, param_size) \
smu               661 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->set_power_profile_mode ? (smu)->ppt_funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
smu               662 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_pre_display_config_changed(smu) \
smu               663 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
smu               664 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_display_config_changed(smu) \
smu               665 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
smu               666 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_apply_clocks_adjust_rules(smu) \
smu               667 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
smu               668 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_notify_smc_dispaly_config(smu) \
smu               669 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
smu               670 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_force_dpm_limit_value(smu, highest) \
smu               671 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
smu               672 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_unforce_dpm_levels(smu) \
smu               673 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
smu               674 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
smu               675 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
smu               676 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_cpu_power_state(smu) \
smu               677 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
smu               678 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_fan_control_mode(smu) \
smu               679 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
smu               680 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_fan_control_mode(smu, value) \
smu               681 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
smu               682 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_fan_speed_percent(smu, speed) \
smu               683 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0)
smu               684 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_fan_speed_percent(smu, speed) \
smu               685 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
smu               686 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_fan_speed_rpm(smu, speed) \
smu               687 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_fan_speed_rpm ? (smu)->ppt_funcs->get_fan_speed_rpm((smu), (speed)) : 0)
smu               689 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_msg_get_index(smu, msg) \
smu               690 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
smu               691 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_clk_get_index(smu, msg) \
smu               692 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index? (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
smu               693 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_feature_get_index(smu, msg) \
smu               694 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)
smu               695 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_table_get_index(smu, tab) \
smu               696 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
smu               697 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_power_get_index(smu, src) \
smu               698 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
smu               699 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_workload_get_type(smu, profile) \
smu               700 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
smu               701 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_run_afll_btc(smu) \
smu               702 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
smu               703 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_allowed_feature_mask(smu, feature_mask, num) \
smu               704 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
smu               705 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_deep_sleep_dcefclk(smu, clk) \
smu               706 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
smu               707 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_active_display_count(smu, count) \
smu               708 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
smu               709 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
smu               710 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
smu               711 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_clock_by_type(smu, type, clocks) \
smu               712 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
smu               713 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_max_high_clocks(smu, clocks) \
smu               714 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
smu               715 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \
smu               716 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) : 0)
smu               717 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
smu               718 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
smu               719 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_display_clock_voltage_request(smu, clock_req) \
smu               720 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
smu               721 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_display_disable_memory_clock_switch(smu, disable_memory_clock_switch) \
smu               722 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->display_disable_memory_clock_switch ? (smu)->ppt_funcs->display_disable_memory_clock_switch((smu), (disable_memory_clock_switch)) : -EINVAL)
smu               723 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_dal_power_level(smu, clocks) \
smu               724 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
smu               725 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_perf_level(smu, designation, level) \
smu               726 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
smu               727 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_current_shallow_sleep_clocks(smu, clocks) \
smu               728 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
smu               729 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_notify_smu_enable_pwe(smu) \
smu               730 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
smu               731 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
smu               732 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
smu               733 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_dpm_set_uvd_enable(smu, enable) \
smu               734 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
smu               735 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_dpm_set_vce_enable(smu, enable) \
smu               736 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
smu               737 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_xgmi_pstate(smu, pstate) \
smu               738 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 		((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
smu               739 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_watermarks_table(smu, tab, clock_ranges) \
smu               740 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
smu               741 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
smu               742 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
smu               743 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_thermal_temperature_range_update(smu, range, rw) \
smu               744 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->thermal_temperature_range_update? (smu)->ppt_funcs->thermal_temperature_range_update((smu), (range), (rw)) : 0)
smu               745 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_thermal_temperature_range(smu, range) \
smu               746 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
smu               747 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_register_irq_handler(smu) \
smu               748 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
smu               749 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_azalia_d3_pme(smu) \
smu               750 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
smu               751 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_dpm_ultimate_freq(smu, param, min, max) \
smu               752 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 		((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
smu               753 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
smu               754 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
smu               755 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
smu               756 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
smu               757 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_baco_is_support(smu) \
smu               758 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false)
smu               759 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_baco_get_state(smu, state) \
smu               760 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
smu               761 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_baco_reset(smu) \
smu               762 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
smu               763 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_asic_set_performance_level(smu, level) \
smu               764 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
smu               765 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_dump_pptable(smu) \
smu               766 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
smu               767 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_dpm_uclk_limited(smu, clock, max) \
smu               768 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 		((smu)->ppt_funcs->get_dpm_uclk_limited ? (smu)->ppt_funcs->get_dpm_uclk_limited((smu), (clock), (max)) : -EINVAL)
smu               771 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
smu               780 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h extern int smu_feature_init_dpm(struct smu_context *smu);
smu               782 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h extern int smu_feature_is_enabled(struct smu_context *smu,
smu               784 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h extern int smu_feature_set_enabled(struct smu_context *smu,
smu               786 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h extern int smu_feature_is_supported(struct smu_context *smu,
smu               788 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h extern int smu_feature_set_supported(struct smu_context *smu,
smu               791 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
smu               796 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_reset(struct smu_context *smu);
smu               797 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
smu               799 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_sys_get_pp_table(struct smu_context *smu, void **table);
smu               800 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size);
smu               801 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
smu               802 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
smu               805 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h extern int smu_display_configuration_change(struct smu_context *smu, const
smu               808 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h extern int smu_get_current_clocks(struct smu_context *smu,
smu               810 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
smu               811 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h extern int smu_handle_task(struct smu_context *smu,
smu               814 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_switch_power_profile(struct smu_context *smu,
smu               817 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version);
smu               818 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
smu               820 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
smu               822 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
smu               824 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
smu               826 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
smu               828 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
smu               829 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
smu               830 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_set_display_count(struct smu_context *smu, uint32_t count);
smu               831 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
smu               832 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
smu               833 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
smu               834 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
smu               835 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
smu               836 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
smu               133 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h void smu_v11_0_set_smu_funcs(struct smu_context *smu);
smu                40 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h void smu_v12_0_set_smu_funcs(struct smu_context *smu);
smu               288 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
smu               303 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static bool is_asic_secure(struct smu_context *smu)
smu               305 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct amdgpu_device *adev = smu->adev;
smu               319 drivers/gpu/drm/amd/powerplay/navi10_ppt.c navi10_get_allowed_feature_mask(struct smu_context *smu,
smu               322 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct amdgpu_device *adev = smu->adev;
smu               365 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
smu               368 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
smu               371 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
smu               376 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if (is_asic_secure(smu)) {
smu               392 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_check_powerplay_table(struct smu_context *smu)
smu               397 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_append_powerplay_table(struct smu_context *smu)
smu               399 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct amdgpu_device *adev = smu->adev;
smu               400 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu               408 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
smu               493 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_store_powerplay_table(struct smu_context *smu)
smu               496 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu               497 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_baco_context *smu_baco = &smu->smu_baco;
smu               518 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
smu               520 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               544 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_metrics_table(struct smu_context *smu,
smu               547 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_table_context *smu_table= &smu->smu_table;
smu               550 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	mutex_lock(&smu->metrics_lock);
smu               552 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
smu               556 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			mutex_unlock(&smu->metrics_lock);
smu               563 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	mutex_unlock(&smu->metrics_lock);
smu               568 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_allocate_dpm_context(struct smu_context *smu)
smu               570 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu               585 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_set_default_dpm_table(struct smu_context *smu)
smu               587 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu               588 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu               624 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
smu               626 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_power_context *smu_power = &smu->smu_power;
smu               632 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
smu               633 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
smu               639 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
smu               640 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
smu               650 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
smu               657 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = navi10_get_metrics_table(smu, &metrics);
smu               661 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	clk_id = smu_clk_get_index(smu, clk_type);
smu               670 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
smu               672 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	PPTable_t *pptable = smu->smu_table.driver_pptable;
smu               676 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	clk_index = smu_clk_get_index(smu, clk_type);
smu               683 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_print_clk_levels(struct smu_context *smu,
smu               699 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
smu               706 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_get_dpm_level_count(smu, clk_type, &count);
smu               710 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
smu               712 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 				ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
smu               720 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
smu               723 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
smu               747 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_force_clk_levels(struct smu_context *smu,
smu               766 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
smu               771 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
smu               775 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
smu               779 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
smu               790 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_populate_umd_state_clk(struct smu_context *smu)
smu               795 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
smu               799 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	smu->pstate_sclk = min_sclk_freq * 100;
smu               801 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL);
smu               805 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	smu->pstate_mclk = min_mclk_freq * 100;
smu               810 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
smu               821 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
smu               829 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
smu               844 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_pre_display_config_changed(struct smu_context *smu)
smu               849 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
smu               853 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
smu               854 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
smu               857 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
smu               865 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_display_config_changed(struct smu_context *smu)
smu               869 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
smu               870 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	    !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
smu               871 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_write_watermarks_table(smu);
smu               875 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		smu->watermarks_bitmap |= WATERMARKS_LOADED;
smu               878 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
smu               879 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
smu               880 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
smu               881 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
smu               882 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 						  smu->display_config->num_display);
smu               890 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
smu               904 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
smu               909 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
smu               917 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_unforce_dpm_levels(struct smu_context *smu)
smu               931 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
smu               935 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
smu               943 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
smu               951 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = navi10_get_metrics_table(smu, &metrics);
smu               960 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_current_activity_percent(struct smu_context *smu,
smu               970 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = navi10_get_metrics_table(smu, &metrics);
smu               989 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static bool navi10_is_dpm_running(struct smu_context *smu)
smu               994 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
smu              1000 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_fan_speed_rpm(struct smu_context *smu,
smu              1009 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = navi10_get_metrics_table(smu, &metrics);
smu              1018 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_fan_speed_percent(struct smu_context *smu,
smu              1024 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	PPTable_t *pptable = smu->smu_table.driver_pptable;
smu              1026 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = navi10_get_fan_speed_rpm(smu, &current_rpm);
smu              1036 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
smu              1072 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		workload_type = smu_workload_get_type(smu, i);
smu              1076 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		result = smu_update_table(smu,
smu              1085 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
smu              1133 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
smu              1138 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	smu->power_profile_mode = input[size];
smu              1140 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
smu              1141 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
smu              1145 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
smu              1149 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_update_table(smu,
smu              1193 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_update_table(smu,
smu              1203 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
smu              1206 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
smu              1212 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_profiling_clk_mask(struct smu_context *smu,
smu              1229 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
smu              1236 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
smu              1243 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
smu              1253 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
smu              1259 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
smu              1260 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
smu              1261 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
smu              1263 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
smu              1266 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		if (!smu_display_clock_voltage_request(smu, &clock_req)) {
smu              1267 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
smu              1268 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 				ret = smu_send_smc_msg_with_param(smu,
smu              1281 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
smu              1282 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
smu              1292 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_set_watermarks_table(struct smu_context *smu,
smu              1352 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_thermal_get_temperature(struct smu_context *smu,
smu              1362 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = navi10_get_metrics_table(smu, &metrics);
smu              1387 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_read_sensor(struct smu_context *smu,
smu              1392 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              1398 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	mutex_lock(&smu->sensor_lock);
smu              1406 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
smu              1410 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = navi10_get_gpu_power(smu, (uint32_t *)data);
smu              1416 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
smu              1420 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_smc_read_sensor(smu, sensor, data, size);
smu              1422 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	mutex_unlock(&smu->sensor_lock);
smu              1427 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
smu              1432 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              1456 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_set_peak_clock_by_device(struct smu_context *smu)
smu              1458 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct amdgpu_device *adev = smu->adev;
smu              1477 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
smu              1480 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, uclk_level - 1, &uclk_freq);
smu              1484 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
smu              1487 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
smu              1494 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
smu              1497 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct amdgpu_device *adev = smu->adev;
smu              1504 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = navi10_set_peak_clock_by_device(smu);
smu              1514 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_thermal_temperature_range(struct smu_context *smu,
smu              1517 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              1529 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
smu              1535 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			smu->smu_table.max_sustainable_clocks;
smu              1536 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
smu              1539 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if(smu->disable_uclk_switch == disable_memory_clock_switch)
smu              1543 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
smu              1545 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
smu              1548 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		smu->disable_uclk_switch = disable_memory_clock_switch;
smu              1553 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_power_limit(struct smu_context *smu,
smu              1557 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	PPTable_t *pptable = smu->smu_table.driver_pptable;
smu              1562 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if (!smu->default_power_limit ||
smu              1563 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	    !smu->power_limit) {
smu              1564 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
smu              1565 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
smu              1569 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
smu              1575 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			smu_read_smc_arg(smu, &asic_default_power_limit);
smu              1586 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		if (smu->od_enabled) {
smu              1587 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
smu              1591 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		smu->default_power_limit = asic_default_power_limit;
smu              1592 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		smu->power_limit = asic_default_power_limit;
smu              1596 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		*limit = smu->default_power_limit;
smu              1598 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		*limit = smu->power_limit;
smu              1643 drivers/gpu/drm/amd/powerplay/navi10_ppt.c void navi10_set_ppt_funcs(struct smu_context *smu)
smu              1645 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu              1647 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	smu->ppt_funcs = &navi10_ppt_funcs;
smu                30 drivers/gpu/drm/amd/powerplay/navi10_ppt.h extern void navi10_set_ppt_funcs(struct smu_context *smu);
smu               141 drivers/gpu/drm/amd/powerplay/renoir_ppt.c static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
smu               143 drivers/gpu/drm/amd/powerplay/renoir_ppt.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               163 drivers/gpu/drm/amd/powerplay/renoir_ppt.c static int renoir_get_dpm_uclk_limited(struct smu_context *smu, uint32_t *clock, bool max)
smu               166 drivers/gpu/drm/amd/powerplay/renoir_ppt.c 	DpmClocks_t *table = smu->smu_table.clocks_table;
smu               180 drivers/gpu/drm/amd/powerplay/renoir_ppt.c static int renoir_print_clk_levels(struct smu_context *smu,
smu               185 drivers/gpu/drm/amd/powerplay/renoir_ppt.c 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
smu               194 drivers/gpu/drm/amd/powerplay/renoir_ppt.c 	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
smu               204 drivers/gpu/drm/amd/powerplay/renoir_ppt.c 		ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max);
smu               266 drivers/gpu/drm/amd/powerplay/renoir_ppt.c void renoir_set_ppt_funcs(struct smu_context *smu)
smu               268 drivers/gpu/drm/amd/powerplay/renoir_ppt.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               270 drivers/gpu/drm/amd/powerplay/renoir_ppt.c 	smu->ppt_funcs = &renoir_ppt_funcs;
smu               271 drivers/gpu/drm/amd/powerplay/renoir_ppt.c 	smu->smc_if_version = SMU12_DRIVER_IF_VERSION;
smu                26 drivers/gpu/drm/amd/powerplay/renoir_ppt.h extern void renoir_set_ppt_funcs(struct smu_context *smu);
smu                56 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
smu                59 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu                64 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
smu                66 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu                72 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_wait_for_response(struct smu_context *smu)
smu                74 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu                91 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
smu                93 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu                96 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	index = smu_msg_get_index(smu, msg);
smu               100 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu_v11_0_wait_for_response(smu);
smu               104 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
smu               106 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_v11_0_wait_for_response(smu);
smu               110 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		       smu_get_message_name(smu, msg), index, ret);
smu               117 drivers/gpu/drm/amd/powerplay/smu_v11_0.c smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
smu               121 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu               124 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	index = smu_msg_get_index(smu, msg);
smu               128 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_v11_0_wait_for_response(smu);
smu               131 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		       smu_get_message_name(smu, msg), index, param, ret);
smu               137 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
smu               139 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_v11_0_wait_for_response(smu);
smu               142 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		       smu_get_message_name(smu, msg), index, param, ret);
smu               147 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_init_microcode(struct smu_context *smu)
smu               149 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu               209 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_load_microcode(struct smu_context *smu)
smu               211 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu               247 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_check_fw_status(struct smu_context *smu)
smu               249 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu               262 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_check_fw_version(struct smu_context *smu)
smu               269 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_get_smc_version(smu, &if_version, &smu_version);
smu               277 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	switch (smu->adev->asic_type) {
smu               279 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_VG20;
smu               282 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
smu               285 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
smu               288 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
smu               291 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
smu               292 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_INV;
smu               304 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (if_version != smu->smc_if_version) {
smu               307 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 			smu->smc_if_version, if_version,
smu               315 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
smu               317 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu               330 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
smu               333 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu               357 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_setup_pptable(struct smu_context *smu)
smu               359 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu               371 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
smu               374 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 			ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
smu               377 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 			ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
smu               378 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 							 smu->smu_table.boot_values.pp_table_id);
smu               391 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev,
smu               398 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu->smu_table.power_play_table)
smu               399 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.power_play_table = table;
smu               400 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu->smu_table.power_play_table_size)
smu               401 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.power_play_table_size = size;
smu               406 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_init_dpm_context(struct smu_context *smu)
smu               408 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu               413 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	return smu_alloc_dpm_context(smu);
smu               416 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
smu               418 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu               436 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_init_smc_tables(struct smu_context *smu)
smu               438 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               452 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_tables_init(smu, tables);
smu               456 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_v11_0_init_dpm_context(smu);
smu               463 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
smu               465 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               478 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_v11_0_fini_dpm_context(smu);
smu               484 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_init_power(struct smu_context *smu)
smu               486 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_power_context *smu_power = &smu->smu_power;
smu               488 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu->pm_enabled)
smu               502 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_fini_power(struct smu_context *smu)
smu               504 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_power_context *smu_power = &smu->smu_power;
smu               506 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu->pm_enabled)
smu               518 drivers/gpu/drm/amd/powerplay/smu_v11_0.c int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
smu               530 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
smu               545 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
smu               546 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
smu               547 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
smu               548 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.socclk = 0;
smu               549 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.dcefclk = 0;
smu               550 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
smu               551 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
smu               552 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
smu               553 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
smu               554 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
smu               555 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.pp_table_id = 0;
smu               560 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
smu               561 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
smu               562 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
smu               563 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.socclk = 0;
smu               564 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.dcefclk = 0;
smu               565 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
smu               566 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
smu               567 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
smu               568 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
smu               569 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
smu               570 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
smu               573 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu->smu_table.boot_values.format_revision = header->format_revision;
smu               574 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu->smu_table.boot_values.content_revision = header->content_revision;
smu               579 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
smu               582 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu               597 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
smu               611 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
smu               625 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
smu               639 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
smu               653 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
smu               655 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if ((smu->smu_table.boot_values.format_revision == 3) &&
smu               656 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	    (smu->smu_table.boot_values.content_revision >= 2)) {
smu               670 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
smu               676 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
smu               678 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               691 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg_with_param(smu,
smu               696 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg_with_param(smu,
smu               706 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
smu               710 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
smu               714 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
smu               722 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_check_pptable(struct smu_context *smu)
smu               726 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_check_powerplay_table(smu);
smu               730 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_parse_pptable(struct smu_context *smu)
smu               734 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_table_context *table_context = &smu->smu_table;
smu               745 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_store_powerplay_table(smu);
smu               749 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_append_powerplay_table(smu);
smu               754 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
smu               758 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_set_default_dpm_table(smu);
smu               763 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_write_pptable(struct smu_context *smu)
smu               765 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_table_context *table_context = &smu->smu_table;
smu               768 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
smu               774 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
smu               777 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               785 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
smu               791 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
smu               795 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg_with_param(smu,
smu               803 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
smu               805 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_table_context *table_context = &smu->smu_table;
smu               807 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu->pm_enabled)
smu               812 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	return smu_set_deep_sleep_dcefclk(smu,
smu               816 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
smu               819 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
smu               822 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_send_smc_msg_with_param(smu,
smu               826 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 			ret = smu_send_smc_msg_with_param(smu,
smu               834 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
smu               838 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu->pm_enabled)
smu               841 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
smu               846 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
smu               848 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_feature *feature = &smu->smu_feature;
smu               858 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
smu               863 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
smu               873 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
smu               882 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
smu               885 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_read_smc_arg(smu, &feature_mask_high);
smu               889 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
smu               892 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_read_smc_arg(smu, &feature_mask_low);
smu               902 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_system_features_control(struct smu_context *smu,
smu               905 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_feature *feature = &smu->smu_feature;
smu               909 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (smu->pm_enabled) {
smu               910 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
smu               916 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
smu               928 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_notify_display_change(struct smu_context *smu)
smu               932 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu->pm_enabled)
smu               934 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
smu               935 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	    smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
smu               936 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
smu               942 drivers/gpu/drm/amd/powerplay/smu_v11_0.c smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
smu               948 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu->pm_enabled)
smu               951 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
smu               952 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	    (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0))
smu               955 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	clk_id = smu_clk_get_index(smu, clock_select);
smu               959 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
smu               966 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_read_smc_arg(smu, clock);
smu               974 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
smu               981 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_read_smc_arg(smu, clock);
smu               986 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
smu               991 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu->smu_table.max_sustainable_clocks)
smu               995 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		max_sustainable_clocks = smu->smu_table.max_sustainable_clocks;
smu               997 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
smu               999 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
smu              1000 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
smu              1001 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
smu              1006 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
smu              1007 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_v11_0_get_max_sustainable_clock(smu,
smu              1017 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
smu              1018 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_v11_0_get_max_sustainable_clock(smu,
smu              1028 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
smu              1029 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_v11_0_get_max_sustainable_clock(smu,
smu              1038 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_v11_0_get_max_sustainable_clock(smu,
smu              1046 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_v11_0_get_max_sustainable_clock(smu,
smu              1054 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_v11_0_get_max_sustainable_clock(smu,
smu              1070 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
smu              1074 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (n > smu->default_power_limit) {
smu              1076 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 				smu->default_power_limit);
smu              1081 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		n = smu->default_power_limit;
smu              1083 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
smu              1088 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
smu              1093 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu->power_limit = n;
smu              1098 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
smu              1109 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	asic_clk_id = smu_clk_get_index(smu, clk_id);
smu              1114 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
smu              1115 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
smu              1117 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
smu              1122 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_read_smc_arg(smu, &freq);
smu              1133 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_thermal_range(struct smu_context *smu,
smu              1136 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu              1163 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
smu              1165 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu              1177 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_start_thermal_control(struct smu_context *smu)
smu              1181 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu              1183 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu->pm_enabled)
smu              1188 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_get_thermal_temperature_range(smu, &range);
smu              1192 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (smu->smu_table.thermal_controller_type) {
smu              1193 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_v11_0_set_thermal_range(smu, range);
smu              1197 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_v11_0_enable_thermal_alert(smu);
smu              1201 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_set_thermal_fan_table(smu);
smu              1224 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
smu              1226 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu              1243 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_read_sensor(struct smu_context *smu,
smu              1254 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
smu              1258 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
smu              1262 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
smu              1270 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_common_read_sensor(smu, sensor, data, size);
smu              1281 drivers/gpu/drm/amd/powerplay/smu_v11_0.c smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
smu              1290 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu->pm_enabled)
smu              1293 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
smu              1294 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
smu              1320 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
smu              1323 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		mutex_lock(&smu->mutex);
smu              1324 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
smu              1325 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		mutex_unlock(&smu->mutex);
smu              1328 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 			smu->hard_min_uclk_req_from_dal = clk_freq;
smu              1336 drivers/gpu/drm/amd/powerplay/smu_v11_0.c smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
smu              1341 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
smu              1344 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu->disable_watermark &&
smu              1345 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	    smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
smu              1346 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	    smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
smu              1347 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu_set_watermarks_table(smu, table, clock_ranges);
smu              1348 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->watermarks_bitmap |= WATERMARKS_EXIST;
smu              1349 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
smu              1355 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
smu              1358 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu              1368 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		mutex_lock(&smu->mutex);
smu              1370 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 			ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
smu              1372 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 			ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
smu              1373 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		mutex_unlock(&smu->mutex);
smu              1383 drivers/gpu/drm/amd/powerplay/smu_v11_0.c smu_v11_0_get_fan_control_mode(struct smu_context *smu)
smu              1385 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
smu              1392 drivers/gpu/drm/amd/powerplay/smu_v11_0.c smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
smu              1396 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
smu              1399 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
smu              1408 drivers/gpu/drm/amd/powerplay/smu_v11_0.c smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
smu              1410 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu              1423 drivers/gpu/drm/amd/powerplay/smu_v11_0.c smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
smu              1425 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu              1432 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (smu_v11_0_auto_fan_control(smu, 0))
smu              1448 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
smu              1452 drivers/gpu/drm/amd/powerplay/smu_v11_0.c smu_v11_0_set_fan_control_mode(struct smu_context *smu,
smu              1459 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_v11_0_set_fan_speed_percent(smu, 100);
smu              1462 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_v11_0_auto_fan_control(smu, 0);
smu              1465 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_v11_0_auto_fan_control(smu, 1);
smu              1479 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
smu              1482 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu              1489 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	mutex_lock(&(smu->mutex));
smu              1490 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_v11_0_auto_fan_control(smu, 0);
smu              1501 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
smu              1504 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	mutex_unlock(&(smu->mutex));
smu              1511 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
smu              1515 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	mutex_lock(&(smu->mutex));
smu              1516 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg_with_param(smu,
smu              1519 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	mutex_unlock(&(smu->mutex));
smu              1566 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_register_irq_handler(struct smu_context *smu)
smu              1568 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu              1569 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_irq_src *irq_src = smu->irq_source;
smu              1579 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu->irq_source = irq_src;
smu              1598 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
smu              1601 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              1628 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
smu              1632 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	mutex_lock(&smu->mutex);
smu              1633 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
smu              1634 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	mutex_unlock(&smu->mutex);
smu              1639 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
smu              1641 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
smu              1644 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static bool smu_v11_0_baco_is_support(struct smu_context *smu)
smu              1646 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu              1647 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_baco_context *smu_baco = &smu->smu_baco;
smu              1658 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
smu              1668 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
smu              1670 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_baco_context *smu_baco = &smu->smu_baco;
smu              1680 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
smu              1683 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct smu_baco_context *smu_baco = &smu->smu_baco;
smu              1686 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (smu_v11_0_baco_get_state(smu) == state)
smu              1692 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, BACO_SEQ_BACO);
smu              1694 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
smu              1704 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_baco_reset(struct smu_context *smu)
smu              1708 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
smu              1712 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
smu              1718 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
smu              1725 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
smu              1731 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	mutex_lock(&smu->mutex);
smu              1732 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	clk_id = smu_clk_get_index(smu, clk_type);
smu              1740 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
smu              1743 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_read_smc_arg(smu, max);
smu              1749 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
smu              1752 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		ret = smu_read_smc_arg(smu, min);
smu              1758 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	mutex_unlock(&smu->mutex);
smu              1814 drivers/gpu/drm/amd/powerplay/smu_v11_0.c void smu_v11_0_set_smu_funcs(struct smu_context *smu)
smu              1816 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	struct amdgpu_device *adev = smu->adev;
smu              1818 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu->funcs = &smu_v11_0_funcs;
smu              1821 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		vega20_set_ppt_funcs(smu);
smu              1824 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		arcturus_set_ppt_funcs(smu);
smu              1829 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		navi10_set_ppt_funcs(smu);
smu                44 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
smu                47 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	struct amdgpu_device *adev = smu->adev;
smu                53 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
smu                55 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	struct amdgpu_device *adev = smu->adev;
smu                61 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_wait_for_response(struct smu_context *smu)
smu                63 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	struct amdgpu_device *adev = smu->adev;
smu                80 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
smu                82 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	struct amdgpu_device *adev = smu->adev;
smu                85 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	index = smu_msg_get_index(smu, msg);
smu                89 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	smu_v12_0_wait_for_response(smu);
smu                93 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	smu_v12_0_send_msg_without_waiting(smu, (uint16_t)index);
smu                95 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	ret = smu_v12_0_wait_for_response(smu);
smu               106 drivers/gpu/drm/amd/powerplay/smu_v12_0.c smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
smu               109 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	struct amdgpu_device *adev = smu->adev;
smu               112 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	index = smu_msg_get_index(smu, msg);
smu               116 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	ret = smu_v12_0_wait_for_response(smu);
smu               125 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	smu_v12_0_send_msg_without_waiting(smu, (uint16_t)index);
smu               127 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	ret = smu_v12_0_wait_for_response(smu);
smu               135 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_check_fw_status(struct smu_context *smu)
smu               137 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	struct amdgpu_device *adev = smu->adev;
smu               150 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_check_fw_version(struct smu_context *smu)
smu               157 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	ret = smu_get_smc_version(smu, &if_version, &smu_version);
smu               173 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	if (if_version != smu->smc_if_version) {
smu               176 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 			smu->smc_if_version, if_version,
smu               184 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
smu               186 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	if (!(smu->adev->flags & AMD_IS_APU))
smu               190 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 		return smu_send_smc_msg(smu, SMU_MSG_PowerDownSdma);
smu               192 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 		return smu_send_smc_msg(smu, SMU_MSG_PowerUpSdma);
smu               195 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
smu               197 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	if (!(smu->adev->flags & AMD_IS_APU))
smu               201 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 		return smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
smu               203 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 		return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn);
smu               206 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
smu               208 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
smu               211 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	return smu_v12_0_send_msg_with_param(smu,
smu               227 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
smu               231 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	struct amdgpu_device *adev = smu->adev;
smu               240 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
smu               245 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 		ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
smu               248 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 		while (!(smu_v12_0_get_gfxoff_status(smu) == 0)) {
smu               257 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 		ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
smu               260 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 		while (!(smu_v12_0_get_gfxoff_status(smu) == 2)) {
smu               273 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_init_smc_tables(struct smu_context *smu)
smu               275 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               288 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	return smu_tables_init(smu, tables);
smu               291 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
smu               293 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               307 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_populate_smc_tables(struct smu_context *smu)
smu               309 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               319 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
smu               322 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
smu               327 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	mutex_lock(&smu->mutex);
smu               333 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 			ret = smu_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency);
smu               338 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 			ret = smu_read_smc_arg(smu, max);
smu               343 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 			ret = smu_get_dpm_uclk_limited(smu, max, true);
smu               358 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 			ret = smu_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency);
smu               363 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 			ret = smu_read_smc_arg(smu, min);
smu               368 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 			ret = smu_get_dpm_uclk_limited(smu, min, false);
smu               379 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	mutex_unlock(&smu->mutex);
smu               399 drivers/gpu/drm/amd/powerplay/smu_v12_0.c void smu_v12_0_set_smu_funcs(struct smu_context *smu)
smu               401 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	struct amdgpu_device *adev = smu->adev;
smu               403 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	smu->funcs = &smu_v12_0_funcs;
smu               407 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 		renoir_set_ppt_funcs(smu);
smu               301 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
smu               316 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
smu               318 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu               342 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_allocate_dpm_context(struct smu_context *smu)
smu               344 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu               377 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_setup_od8_information(struct smu_context *smu)
smu               380 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu               381 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct vega20_od8_settings *od8_settings = (struct vega20_od8_settings *)smu->od_settings;
smu               453 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_store_powerplay_table(struct smu_context *smu)
smu               456 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu               472 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_append_powerplay_table(struct smu_context *smu)
smu               474 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu               482 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
smu               563 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_check_powerplay_table(struct smu_context *smu)
smu               566 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu               583 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_run_btc_afll(struct smu_context *smu)
smu               585 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
smu               590 drivers/gpu/drm/amd/powerplay/vega20_ppt.c vega20_get_allowed_feature_mask(struct smu_context *smu,
smu               628 drivers/gpu/drm/amd/powerplay/vega20_ppt.c amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
smu               631 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
smu               637 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	mutex_lock(&(smu->mutex));
smu               655 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	mutex_unlock(&(smu->mutex));
smu               661 drivers/gpu/drm/amd/powerplay/vega20_ppt.c vega20_set_single_dpm_table(struct smu_context *smu,
smu               668 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = smu_send_smc_msg_with_param(smu,
smu               676 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	smu_read_smc_arg(smu, &num_of_levels);
smu               685 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_send_smc_msg_with_param(smu,
smu               692 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		smu_read_smc_arg(smu, &clk);
smu               711 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_set_default_dpm_table(struct smu_context *smu)
smu               715 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu               724 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
smu               725 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_set_single_dpm_table(smu, single_dpm_table,
smu               733 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
smu               740 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
smu               741 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_set_single_dpm_table(smu, single_dpm_table,
smu               749 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
smu               756 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
smu               757 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_set_single_dpm_table(smu, single_dpm_table,
smu               765 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
smu               772 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT)) {
smu               773 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
smu               780 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
smu               787 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
smu               788 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
smu               795 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
smu               802 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
smu               803 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
smu               810 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
smu               817 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
smu               818 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_set_single_dpm_table(smu, single_dpm_table,
smu               826 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
smu               833 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
smu               834 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_set_single_dpm_table(smu, single_dpm_table,
smu               848 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
smu               849 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_set_single_dpm_table(smu, single_dpm_table,
smu               863 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
smu               864 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_set_single_dpm_table(smu, single_dpm_table,
smu               878 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
smu               879 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_set_single_dpm_table(smu, single_dpm_table,
smu               896 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_populate_umd_state_clk(struct smu_context *smu)
smu               898 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu               907 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	smu->pstate_sclk = gfx_table->dpm_levels[0].value;
smu               908 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	smu->pstate_mclk = mem_table->dpm_levels[0].value;
smu               912 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		smu->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
smu               913 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		smu->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
smu               916 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	smu->pstate_sclk = smu->pstate_sclk * 100;
smu               917 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	smu->pstate_mclk = smu->pstate_mclk * 100;
smu               922 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_clk_table(struct smu_context *smu,
smu               940 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_print_clk_levels(struct smu_context *smu,
smu               946 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct amdgpu_device *adev = smu->adev;
smu               949 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu               950 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu               953 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		(struct vega20_od8_settings *)smu->od_settings;
smu               962 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
smu               969 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
smu               983 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
smu               990 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
smu              1004 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
smu              1011 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
smu              1025 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
smu              1040 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now);
smu              1047 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
smu              1138 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 			ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
smu              1183 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_upload_dpm_level(struct smu_context *smu, bool max,
smu              1191 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	dpm_table = smu->smu_dpm.dpm_context;
smu              1193 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
smu              1198 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_send_smc_msg_with_param(smu,
smu              1208 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
smu              1213 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_send_smc_msg_with_param(smu,
smu              1223 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
smu              1228 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_send_smc_msg_with_param(smu,
smu              1238 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT) &&
smu              1243 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_send_smc_msg_with_param(smu,
smu              1253 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
smu              1258 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 			ret = smu_send_smc_msg_with_param(smu,
smu              1271 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_force_clk_levels(struct smu_context *smu,
smu              1277 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu              1285 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	mutex_lock(&(smu->mutex));
smu              1290 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	dpm_table = smu->smu_dpm.dpm_context;
smu              1308 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
smu              1314 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
smu              1335 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
smu              1341 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
smu              1362 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
smu              1368 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
smu              1389 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
smu              1395 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
smu              1415 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_DCEFCLK_MASK);
smu              1428 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_send_smc_msg_with_param(smu,
smu              1439 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	mutex_unlock(&(smu->mutex));
smu              1443 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
smu              1449 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu              1454 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	mutex_lock(&smu->mutex);
smu              1459 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
smu              1463 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
smu              1467 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
smu              1471 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
smu              1477 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	mutex_unlock(&smu->mutex);
smu              1481 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
smu              1487 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = smu_send_smc_msg_with_param(smu,
smu              1495 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	smu_read_smc_arg(smu, voltage);
smu              1501 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_set_default_od8_setttings(struct smu_context *smu)
smu              1503 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              1509 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu->od_settings)
smu              1517 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	smu->od_settings = (void *)od8_settings;
smu              1519 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = vega20_setup_od8_information(smu);
smu              1525 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
smu              1571 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 			ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
smu              1579 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 			ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
smu              1587 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 			ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
smu              1598 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
smu              1622 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) {
smu              1646 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_THERMAL_BIT)) {
smu              1688 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_metrics_table(struct smu_context *smu,
smu              1691 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *smu_table= &smu->smu_table;
smu              1694 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	mutex_lock(&smu->metrics_lock);
smu              1696 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
smu              1700 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 			mutex_unlock(&smu->metrics_lock);
smu              1707 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	mutex_unlock(&smu->metrics_lock);
smu              1712 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_set_default_od_settings(struct smu_context *smu,
smu              1715 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              1727 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
smu              1734 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_set_default_od8_setttings(smu);
smu              1739 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
smu              1749 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_od_percentage(struct smu_context *smu,
smu              1752 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu              1785 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
smu              1812 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (!smu->pm_enabled || !buf)
smu              1821 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		workload_type = smu_workload_get_type(smu, i);
smu              1825 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		result = smu_update_table(smu,
smu              1834 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 			i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
smu              1896 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
smu              1901 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	smu->power_profile_mode = input[size];
smu              1903 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (!smu->pm_enabled)
smu              1905 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
smu              1906 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
smu              1910 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
smu              1911 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_update_table(smu,
smu              1966 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_update_table(smu,
smu              1976 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
smu              1979 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
smu              1986 drivers/gpu/drm/amd/powerplay/vega20_ppt.c vega20_get_profiling_clk_mask(struct smu_context *smu,
smu              1992 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
smu              1997 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (!smu->smu_dpm.dpm_context)
smu              2030 drivers/gpu/drm/amd/powerplay/vega20_ppt.c vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
smu              2034 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
smu              2038 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
smu              2050 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_send_smc_msg_with_param(smu,
smu              2062 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_pre_display_config_changed(struct smu_context *smu)
smu              2065 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
smu              2067 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (!smu->smu_dpm.dpm_context)
smu              2070 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
smu              2071 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = vega20_set_uclk_to_highest_dpm_level(smu,
smu              2078 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_display_config_changed(struct smu_context *smu)
smu              2082 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
smu              2083 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	    !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
smu              2084 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_write_watermarks_table(smu);
smu              2089 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		smu->watermarks_bitmap |= WATERMARKS_LOADED;
smu              2092 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
smu              2093 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
smu              2094 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
smu              2095 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		smu_send_smc_msg_with_param(smu,
smu              2097 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 					    smu->display_config->num_display);
smu              2103 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
smu              2105 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
smu              2112 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	disable_mclk_switching = ((1 < smu->display_config->num_display) &&
smu              2113 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 				  !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
smu              2114 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
smu              2161 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
smu              2162 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
smu              2169 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 				if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
smu              2177 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu->display_config->nb_pstate_switch_disable)
smu              2251 drivers/gpu/drm/amd/powerplay/vega20_ppt.c vega20_notify_smc_dispaly_config(struct smu_context *smu)
smu              2253 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
smu              2259 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
smu              2260 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
smu              2261 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
smu              2263 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
smu              2266 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
smu              2267 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 			if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
smu              2268 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 				ret = smu_send_smc_msg_with_param(smu,
smu              2281 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
smu              2283 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_send_smc_msg_with_param(smu,
smu              2340 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
smu              2345 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		(struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
smu              2374 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
smu              2381 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
smu              2391 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_unforce_dpm_levels(struct smu_context *smu)
smu              2396 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		(struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
smu              2419 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
smu              2425 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
smu              2434 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_update_specified_od8_value(struct smu_context *smu,
smu              2438 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              2442 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		(struct vega20_od8_settings *)smu->od_settings;
smu              2511 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_update_od8_settings(struct smu_context *smu,
smu              2515 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              2518 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
smu              2525 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = vega20_update_specified_od8_value(smu, index, value);
smu              2529 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
smu              2539 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_set_od_percentage(struct smu_context *smu,
smu              2543 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu              2553 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	mutex_lock(&(smu->mutex));
smu              2562 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT);
smu              2569 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT);
smu              2585 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = vega20_update_od8_settings(smu, index, od_clk);
smu              2592 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_set_single_dpm_table(smu, single_dpm_table,
smu              2600 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
smu              2603 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = smu_handle_task(smu, smu_dpm->dpm_level,
smu              2607 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	mutex_unlock(&(smu->mutex));
smu              2612 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_odn_edit_dpm_table(struct smu_context *smu,
smu              2616 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              2619 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
smu              2623 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		(struct vega20_od8_settings *)smu->od_settings;
smu              2686 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
smu              2793 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
smu              2802 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
smu              2813 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 			if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
smu              2814 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 				ret = vega20_set_single_dpm_table(smu, single_dpm_table,
smu              2822 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 				single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
smu              2833 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		mutex_lock(&(smu->mutex));
smu              2834 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_handle_task(smu, smu_dpm->dpm_level,
smu              2836 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		mutex_unlock(&(smu->mutex));
smu              2842 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
smu              2844 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_UVD_BIT))
smu              2847 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT))
smu              2850 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_UVD_BIT, enable);
smu              2853 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
smu              2855 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_VCE_BIT))
smu              2858 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT))
smu              2861 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
smu              2864 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static bool vega20_is_dpm_running(struct smu_context *smu)
smu              2869 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
smu              2875 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_set_thermal_fan_table(struct smu_context *smu)
smu              2878 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              2881 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
smu              2887 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_fan_speed_rpm(struct smu_context *smu,
smu              2892 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
smu              2899 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	smu_read_smc_arg(smu, speed);
smu              2904 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_fan_speed_percent(struct smu_context *smu,
smu              2909 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	PPTable_t *pptable = smu->smu_table.driver_pptable;
smu              2911 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = vega20_get_fan_speed_rpm(smu, &current_rpm);
smu              2921 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
smu              2930 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = vega20_get_metrics_table(smu, &metrics);
smu              2934 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = smu_get_smc_version(smu, NULL, &smu_version);
smu              2947 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_current_activity_percent(struct smu_context *smu,
smu              2957 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = vega20_get_metrics_table(smu, &metrics);
smu              2976 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_thermal_get_temperature(struct smu_context *smu,
smu              2980 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct amdgpu_device *adev = smu->adev;
smu              2988 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = vega20_get_metrics_table(smu, &metrics);
smu              3018 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_read_sensor(struct smu_context *smu,
smu              3023 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              3029 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	mutex_lock(&smu->sensor_lock);
smu              3037 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_get_current_activity_percent(smu,
smu              3043 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_get_gpu_power(smu, (uint32_t *)data);
smu              3049 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = vega20_thermal_get_temperature(smu, sensor, (uint32_t *)data);
smu              3053 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		ret = smu_smc_read_sensor(smu, sensor, data, size);
smu              3055 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	mutex_unlock(&smu->sensor_lock);
smu              3060 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_set_watermarks_table(struct smu_context *smu,
smu              3120 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_thermal_temperature_range(struct smu_context *smu,
smu              3123 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *table_context = &smu->smu_table;
smu              3125 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	PPTable_t *pptable = smu->smu_table.driver_pptable;
smu              3192 drivers/gpu/drm/amd/powerplay/vega20_ppt.c void vega20_set_ppt_funcs(struct smu_context *smu)
smu              3194 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_table_context *smu_table = &smu->smu_table;
smu              3196 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	smu->ppt_funcs = &vega20_ppt_funcs;
smu               177 drivers/gpu/drm/amd/powerplay/vega20_ppt.h extern void vega20_set_ppt_funcs(struct smu_context *smu);
smu                99 drivers/macintosh/smu.c static struct smu_device	*smu;
smu               115 drivers/macintosh/smu.c 	if (list_empty(&smu->cmd_list))
smu               119 drivers/macintosh/smu.c 	cmd = list_entry(smu->cmd_list.next, struct smu_cmd, link);
smu               120 drivers/macintosh/smu.c 	smu->cmd_cur = cmd;
smu               128 drivers/macintosh/smu.c 	smu->cmd_buf->cmd = cmd->cmd;
smu               129 drivers/macintosh/smu.c 	smu->cmd_buf->length = cmd->data_len;
smu               130 drivers/macintosh/smu.c 	memcpy(smu->cmd_buf->data, cmd->data_buf, cmd->data_len);
smu               133 drivers/macintosh/smu.c 	faddr = (unsigned long)smu->cmd_buf;
smu               134 drivers/macintosh/smu.c 	fend = faddr + smu->cmd_buf->length + 2;
smu               147 drivers/macintosh/smu.c 	if (smu->broken_nap)
smu               154 drivers/macintosh/smu.c 	writel(smu->cmd_buf_abs, smu->db_buf);
smu               157 drivers/macintosh/smu.c 	pmac_do_feature_call(PMAC_FTR_WRITE_GPIO, NULL, smu->doorbell, 4);
smu               173 drivers/macintosh/smu.c 	spin_lock_irqsave(&smu->lock, flags);
smu               175 drivers/macintosh/smu.c 	gpio = pmac_do_feature_call(PMAC_FTR_READ_GPIO, NULL, smu->doorbell);
smu               177 drivers/macintosh/smu.c 		spin_unlock_irqrestore(&smu->lock, flags);
smu               181 drivers/macintosh/smu.c 	cmd = smu->cmd_cur;
smu               182 drivers/macintosh/smu.c 	smu->cmd_cur = NULL;
smu               196 drivers/macintosh/smu.c 		faddr = (unsigned long)smu->cmd_buf;
smu               201 drivers/macintosh/smu.c 		if (ack != smu->cmd_buf->cmd) {
smu               203 drivers/macintosh/smu.c 				ack, smu->cmd_buf->cmd);
smu               206 drivers/macintosh/smu.c 		reply_len = rc == 0 ? smu->cmd_buf->length : 0;
smu               216 drivers/macintosh/smu.c 			memcpy(cmd->reply_buf, smu->cmd_buf->data, reply_len);
smu               228 drivers/macintosh/smu.c 	if (smu->broken_nap)
smu               233 drivers/macintosh/smu.c 	spin_unlock_irqrestore(&smu->lock, flags);
smu               267 drivers/macintosh/smu.c 	if (smu == NULL)
smu               274 drivers/macintosh/smu.c 	spin_lock_irqsave(&smu->lock, flags);
smu               275 drivers/macintosh/smu.c 	list_add_tail(&cmd->link, &smu->cmd_list);
smu               276 drivers/macintosh/smu.c 	if (smu->cmd_cur == NULL)
smu               278 drivers/macintosh/smu.c 	spin_unlock_irqrestore(&smu->lock, flags);
smu               281 drivers/macintosh/smu.c 	if (!smu_irq_inited || !smu->db_irq)
smu               324 drivers/macintosh/smu.c 	if (smu == NULL)
smu               327 drivers/macintosh/smu.c 	gpio = pmac_do_feature_call(PMAC_FTR_READ_GPIO, NULL, smu->doorbell);
smu               329 drivers/macintosh/smu.c 		smu_db_intr(smu->db_irq, smu);
smu               385 drivers/macintosh/smu.c 	if (smu == NULL)
smu               412 drivers/macintosh/smu.c 	if (smu == NULL)
smu               436 drivers/macintosh/smu.c 	if (smu == NULL)
smu               452 drivers/macintosh/smu.c 	if (smu == NULL)
smu               466 drivers/macintosh/smu.c 	return smu != NULL;
smu               494 drivers/macintosh/smu.c 	smu = memblock_alloc(sizeof(struct smu_device), SMP_CACHE_BYTES);
smu               495 drivers/macintosh/smu.c 	if (!smu)
smu               499 drivers/macintosh/smu.c 	spin_lock_init(&smu->lock);
smu               500 drivers/macintosh/smu.c 	INIT_LIST_HEAD(&smu->cmd_list);
smu               501 drivers/macintosh/smu.c 	INIT_LIST_HEAD(&smu->cmd_i2c_list);
smu               502 drivers/macintosh/smu.c 	smu->of_node = np;
smu               503 drivers/macintosh/smu.c 	smu->db_irq = 0;
smu               504 drivers/macintosh/smu.c 	smu->msg_irq = 0;
smu               509 drivers/macintosh/smu.c 	smu->cmd_buf_abs = (u32)smu_cmdbuf_abs;
smu               510 drivers/macintosh/smu.c 	smu->cmd_buf = __va(smu_cmdbuf_abs);
smu               512 drivers/macintosh/smu.c 	smu->db_node = of_find_node_by_name(NULL, "smu-doorbell");
smu               513 drivers/macintosh/smu.c 	if (smu->db_node == NULL) {
smu               518 drivers/macintosh/smu.c 	data = of_get_property(smu->db_node, "reg", NULL);
smu               529 drivers/macintosh/smu.c 	smu->doorbell = *data;
smu               530 drivers/macintosh/smu.c 	if (smu->doorbell < 0x50)
smu               531 drivers/macintosh/smu.c 		smu->doorbell += 0x50;
smu               535 drivers/macintosh/smu.c 		smu->msg_node = of_find_node_by_name(NULL, "smu-interrupt");
smu               536 drivers/macintosh/smu.c 		if (smu->msg_node == NULL)
smu               538 drivers/macintosh/smu.c 		data = of_get_property(smu->msg_node, "reg", NULL);
smu               540 drivers/macintosh/smu.c 			of_node_put(smu->msg_node);
smu               541 drivers/macintosh/smu.c 			smu->msg_node = NULL;
smu               544 drivers/macintosh/smu.c 		smu->msg = *data;
smu               545 drivers/macintosh/smu.c 		if (smu->msg < 0x50)
smu               546 drivers/macintosh/smu.c 			smu->msg += 0x50;
smu               553 drivers/macintosh/smu.c 	smu->db_buf = ioremap(0x8000860c, 0x1000);
smu               554 drivers/macintosh/smu.c 	if (smu->db_buf == NULL) {
smu               561 drivers/macintosh/smu.c 	smu->broken_nap = pmac_get_uninorth_variant() < 4;
smu               562 drivers/macintosh/smu.c 	if (smu->broken_nap)
smu               569 drivers/macintosh/smu.c 	of_node_put(smu->msg_node);
smu               571 drivers/macintosh/smu.c 	of_node_put(smu->db_node);
smu               573 drivers/macintosh/smu.c 	memblock_free(__pa(smu), sizeof(struct smu_device));
smu               574 drivers/macintosh/smu.c 	smu = NULL;
smu               583 drivers/macintosh/smu.c 	if (!smu)
smu               586 drivers/macintosh/smu.c 	timer_setup(&smu->i2c_timer, smu_i2c_retry, 0);
smu               588 drivers/macintosh/smu.c 	if (smu->db_node) {
smu               589 drivers/macintosh/smu.c 		smu->db_irq = irq_of_parse_and_map(smu->db_node, 0);
smu               590 drivers/macintosh/smu.c 		if (!smu->db_irq)
smu               592 drivers/macintosh/smu.c 			       smu->db_node);
smu               594 drivers/macintosh/smu.c 	if (smu->msg_node) {
smu               595 drivers/macintosh/smu.c 		smu->msg_irq = irq_of_parse_and_map(smu->msg_node, 0);
smu               596 drivers/macintosh/smu.c 		if (!smu->msg_irq)
smu               598 drivers/macintosh/smu.c 			       smu->msg_node);
smu               605 drivers/macintosh/smu.c 	if (smu->db_irq) {
smu               606 drivers/macintosh/smu.c 		if (request_irq(smu->db_irq, smu_db_intr,
smu               607 drivers/macintosh/smu.c 				IRQF_SHARED, "SMU doorbell", smu) < 0) {
smu               610 drivers/macintosh/smu.c 			       smu->db_irq);
smu               611 drivers/macintosh/smu.c 			smu->db_irq = 0;
smu               615 drivers/macintosh/smu.c 	if (smu->msg_irq) {
smu               616 drivers/macintosh/smu.c 		if (request_irq(smu->msg_irq, smu_msg_intr,
smu               617 drivers/macintosh/smu.c 				IRQF_SHARED, "SMU message", smu) < 0) {
smu               620 drivers/macintosh/smu.c 			       smu->msg_irq);
smu               621 drivers/macintosh/smu.c 			smu->msg_irq = 0;
smu               641 drivers/macintosh/smu.c 	for (np = NULL; (np = of_get_next_child(smu->of_node, np)) != NULL;)
smu               644 drivers/macintosh/smu.c 						  &smu->of_dev->dev);
smu               651 drivers/macintosh/smu.c 	if (!smu)
smu               653 drivers/macintosh/smu.c 	smu->of_dev = dev;
smu               696 drivers/macintosh/smu.c 	if (!smu)
smu               698 drivers/macintosh/smu.c 	return smu->of_dev;
smu               728 drivers/macintosh/smu.c 	spin_lock_irqsave(&smu->lock, flags);
smu               729 drivers/macintosh/smu.c 	smu->cmd_i2c_cur = NULL;
smu               734 drivers/macintosh/smu.c 	if (!list_empty(&smu->cmd_i2c_list)) {
smu               738 drivers/macintosh/smu.c 		newcmd = list_entry(smu->cmd_i2c_list.next,
smu               740 drivers/macintosh/smu.c 		smu->cmd_i2c_cur = newcmd;
smu               744 drivers/macintosh/smu.c 		list_add_tail(&cmd->scmd.link, &smu->cmd_list);
smu               745 drivers/macintosh/smu.c 		if (smu->cmd_cur == NULL)
smu               748 drivers/macintosh/smu.c 	spin_unlock_irqrestore(&smu->lock, flags);
smu               759 drivers/macintosh/smu.c 	struct smu_i2c_cmd	*cmd = smu->cmd_i2c_cur;
smu               794 drivers/macintosh/smu.c 		BUG_ON(cmd != smu->cmd_i2c_cur);
smu               800 drivers/macintosh/smu.c 		mod_timer(&smu->i2c_timer, jiffies + msecs_to_jiffies(5));
smu               828 drivers/macintosh/smu.c 	if (smu == NULL)
smu               887 drivers/macintosh/smu.c 	spin_lock_irqsave(&smu->lock, flags);
smu               888 drivers/macintosh/smu.c 	if (smu->cmd_i2c_cur == NULL) {
smu               889 drivers/macintosh/smu.c 		smu->cmd_i2c_cur = cmd;
smu               890 drivers/macintosh/smu.c 		list_add_tail(&cmd->scmd.link, &smu->cmd_list);
smu               891 drivers/macintosh/smu.c 		if (smu->cmd_cur == NULL)
smu               894 drivers/macintosh/smu.c 		list_add_tail(&cmd->link, &smu->cmd_i2c_list);
smu               895 drivers/macintosh/smu.c 	spin_unlock_irqrestore(&smu->lock, flags);
smu               960 drivers/macintosh/smu.c 	DPRINTK("SMU: Query partition infos ... (irq=%d)\n", smu->db_irq);
smu              1003 drivers/macintosh/smu.c 	if (of_add_property(smu->of_node, prop)) {
smu              1024 drivers/macintosh/smu.c 	if (!smu)
smu              1039 drivers/macintosh/smu.c 	part = of_get_property(smu->of_node, pname, size);
smu              1331 drivers/macintosh/smu.c 	if (!smu)
smu               258 drivers/macintosh/windfarm_smu_controls.c 	struct device_node *smu, *fans, *fan;
smu               263 drivers/macintosh/windfarm_smu_controls.c 	smu = of_find_node_by_type(NULL, "smu");
smu               264 drivers/macintosh/windfarm_smu_controls.c 	if (smu == NULL)
smu               268 drivers/macintosh/windfarm_smu_controls.c 	for (fans = NULL; (fans = of_get_next_child(smu, fans)) != NULL;)
smu               288 drivers/macintosh/windfarm_smu_controls.c 	for (fans = NULL; (fans = of_get_next_child(smu, fans)) != NULL;)
smu               304 drivers/macintosh/windfarm_smu_controls.c 	of_node_put(smu);
smu               410 drivers/macintosh/windfarm_smu_sensors.c 	struct device_node *smu, *sensors, *s;
smu               419 drivers/macintosh/windfarm_smu_sensors.c 	smu = of_find_node_by_type(NULL, "smu");
smu               420 drivers/macintosh/windfarm_smu_sensors.c 	if (smu == NULL)
smu               425 drivers/macintosh/windfarm_smu_sensors.c 	     (sensors = of_get_next_child(smu, sensors)) != NULL;)
smu               429 drivers/macintosh/windfarm_smu_sensors.c 	of_node_put(smu);
smu               175 drivers/mtd/nand/raw/atmel/pmecc.c 	s16 *smu;
smu               374 drivers/mtd/nand/raw/atmel/pmecc.c 	user->smu = user->lmu + (req->ecc.strength + 1);
smu               375 drivers/mtd/nand/raw/atmel/pmecc.c 	user->mu = (s32 *)PTR_ALIGN(user->smu +
smu               502 drivers/mtd/nand/raw/atmel/pmecc.c 	s16 *smu = user->smu;
smu               516 drivers/mtd/nand/raw/atmel/pmecc.c 	memset(smu, 0, sizeof(s16) * num);
smu               517 drivers/mtd/nand/raw/atmel/pmecc.c 	smu[0] = 1;
smu               530 drivers/mtd/nand/raw/atmel/pmecc.c 	memset(&smu[num], 0, sizeof(s16) * num);
smu               531 drivers/mtd/nand/raw/atmel/pmecc.c 	smu[num] = 1;
smu               542 drivers/mtd/nand/raw/atmel/pmecc.c 	memset(&smu[(strength + 1) * num], 0, sizeof(s16) * num);
smu               559 drivers/mtd/nand/raw/atmel/pmecc.c 					smu[(strength + 1) * num + j] =
smu               560 drivers/mtd/nand/raw/atmel/pmecc.c 							smu[i * num + j];
smu               568 drivers/mtd/nand/raw/atmel/pmecc.c 				smu[(i + 1) * num + j] = smu[i * num + j];
smu               594 drivers/mtd/nand/raw/atmel/pmecc.c 				smu[(i + 1) * num + k] = 0;
smu               600 drivers/mtd/nand/raw/atmel/pmecc.c 				if (!(smu[ro * num + k] && dmu[i]))
smu               605 drivers/mtd/nand/raw/atmel/pmecc.c 				c = index_of[smu[ro * num + k]];
smu               608 drivers/mtd/nand/raw/atmel/pmecc.c 				smu[(i + 1) * num + (k + diff)] = a;
smu               612 drivers/mtd/nand/raw/atmel/pmecc.c 				smu[(i + 1) * num + k] ^= smu[i * num + k];
smu               627 drivers/mtd/nand/raw/atmel/pmecc.c 			} else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
smu               630 drivers/mtd/nand/raw/atmel/pmecc.c 				a = index_of[smu[(i + 1) * num + k]];
smu               649 drivers/mtd/nand/raw/atmel/pmecc.c 	s16 *smu = user->smu;
smu               655 drivers/mtd/nand/raw/atmel/pmecc.c 		writel_relaxed(smu[(strength + 1) * num + i],