smpl_phase        217 drivers/mmc/host/dw_mmc-k3.c 				     int smpl_phase)
smpl_phase        232 drivers/mmc/host/dw_mmc-k3.c 	if (smpl_phase == -1)
smpl_phase        233 drivers/mmc/host/dw_mmc-k3.c 		smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
smpl_phase        238 drivers/mmc/host/dw_mmc-k3.c 		if (smpl_phase >= USE_DLY_MIN_SMPL &&
smpl_phase        239 drivers/mmc/host/dw_mmc-k3.c 				smpl_phase <= USE_DLY_MAX_SMPL)
smpl_phase        243 drivers/mmc/host/dw_mmc-k3.c 		if (smpl_phase >= ENABLE_SHIFT_MIN_SMPL &&
smpl_phase        244 drivers/mmc/host/dw_mmc-k3.c 				smpl_phase <= ENABLE_SHIFT_MAX_SMPL)
smpl_phase        252 drivers/mmc/host/dw_mmc-k3.c 	reg_value = FIELD_PREP(UHS_REG_EXT_SAMPLE_PHASE_MASK, smpl_phase) |
smpl_phase        372 drivers/mmc/host/dw_mmc-k3.c 	int smpl_phase = 0;
smpl_phase        376 drivers/mmc/host/dw_mmc-k3.c 	for (i = 0; i < NUM_PHASES; ++i, ++smpl_phase) {
smpl_phase        377 drivers/mmc/host/dw_mmc-k3.c 		smpl_phase %= 32;
smpl_phase        380 drivers/mmc/host/dw_mmc-k3.c 		dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase);
smpl_phase        383 drivers/mmc/host/dw_mmc-k3.c 			tuning_sample_flag |= (1 << smpl_phase);
smpl_phase        385 drivers/mmc/host/dw_mmc-k3.c 			tuning_sample_flag &= ~(1 << smpl_phase);