smcr 704 arch/arm/common/sa1111.c unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC); smcr 707 arch/arm/common/sa1111.c smcr |= SMCR_CLAT; smcr 709 arch/arm/common/sa1111.c writel_relaxed(smcr, sachip->base + SA1111_SMCR); smcr 86 drivers/counter/stm32-timer-cnt.c u32 smcr; smcr 88 drivers/counter/stm32-timer-cnt.c regmap_read(priv->regmap, TIM_SMCR, &smcr); smcr 90 drivers/counter/stm32-timer-cnt.c switch (smcr & TIM_SMCR_SMS) { smcr 173 drivers/i2c/busses/i2c-highlander.c u16 smcr; smcr 177 drivers/i2c/busses/i2c-highlander.c smcr = ioread16(dev->base + SMCR); smcr 185 drivers/i2c/busses/i2c-highlander.c if (smcr & SMCR_IRIC) smcr 526 drivers/iio/trigger/stm32-timer-trigger.c u32 smcr; smcr 528 drivers/iio/trigger/stm32-timer-trigger.c regmap_read(priv->regmap, TIM_SMCR, &smcr); smcr 530 drivers/iio/trigger/stm32-timer-trigger.c return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL; smcr 603 drivers/iio/trigger/stm32-timer-trigger.c u32 smcr; smcr 605 drivers/iio/trigger/stm32-timer-trigger.c regmap_read(priv->regmap, TIM_SMCR, &smcr); smcr 606 drivers/iio/trigger/stm32-timer-trigger.c smcr &= TIM_SMCR_SMS; smcr 608 drivers/iio/trigger/stm32-timer-trigger.c return stm32_sms2enable_mode(smcr); smcr 160 drivers/memory/jz4780-nemc.c uint32_t smcr, val, cycles; smcr 185 drivers/memory/jz4780-nemc.c smcr = readl(nemc->base + NEMC_SMCRn(bank)); smcr 186 drivers/memory/jz4780-nemc.c smcr &= ~NEMC_SMCR_SMT; smcr 189 drivers/memory/jz4780-nemc.c smcr &= ~NEMC_SMCR_BW_MASK; smcr 192 drivers/memory/jz4780-nemc.c smcr |= NEMC_SMCR_BW_8; smcr 205 drivers/memory/jz4780-nemc.c smcr &= ~NEMC_SMCR_TAS_MASK; smcr 213 drivers/memory/jz4780-nemc.c smcr |= cycles << NEMC_SMCR_TAS_SHIFT; smcr 217 drivers/memory/jz4780-nemc.c smcr &= ~NEMC_SMCR_TAH_MASK; smcr 225 drivers/memory/jz4780-nemc.c smcr |= cycles << NEMC_SMCR_TAH_SHIFT; smcr 229 drivers/memory/jz4780-nemc.c smcr &= ~NEMC_SMCR_TBP_MASK; smcr 237 drivers/memory/jz4780-nemc.c smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TBP_SHIFT; smcr 241 drivers/memory/jz4780-nemc.c smcr &= ~NEMC_SMCR_TAW_MASK; smcr 249 drivers/memory/jz4780-nemc.c smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TAW_SHIFT; smcr 253 drivers/memory/jz4780-nemc.c smcr &= ~NEMC_SMCR_TSTRV_MASK; smcr 261 drivers/memory/jz4780-nemc.c smcr |= cycles << NEMC_SMCR_TSTRV_SHIFT; smcr 264 drivers/memory/jz4780-nemc.c writel(smcr, nemc->base + NEMC_SMCRn(bank));