smc_state_table 953 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 1469 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.pp_table.UlvOffsetVid = smc_state_table 1472 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.pp_table.UlvSmnclkDid = smc_state_table 1474 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.pp_table.UlvMp1clkDid = smc_state_table 1476 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.pp_table.UlvGfxclkBypass = smc_state_table 1478 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 = smc_state_table 1480 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 = smc_state_table 1507 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 1665 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 1720 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 1813 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 1856 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 1951 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 2014 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 2085 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 2104 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 2340 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 2426 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table); smc_state_table 2498 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 3495 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (data->smc_state_table.gfx_boot_level != smc_state_table 3499 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_boot_level); smc_state_table 3501 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_boot_level; smc_state_table 3506 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (data->smc_state_table.mem_boot_level != smc_state_table 3508 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) { smc_state_table 3516 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_boot_level); smc_state_table 3519 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_boot_level; smc_state_table 3524 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (data->smc_state_table.soc_boot_level != smc_state_table 3528 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.soc_boot_level); smc_state_table 3530 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.soc_boot_level; smc_state_table 3544 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (data->smc_state_table.gfx_max_level != smc_state_table 3548 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_max_level); smc_state_table 3550 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_max_level; smc_state_table 3555 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (data->smc_state_table.mem_max_level != smc_state_table 3559 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_max_level); smc_state_table 3561 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_max_level; smc_state_table 3566 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (data->smc_state_table.soc_max_level != smc_state_table 3570 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.soc_max_level); smc_state_table 3572 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.soc_max_level; smc_state_table 3593 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_boot_level = smc_state_table 3595 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_max_level = smc_state_table 3597 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_boot_level = smc_state_table 3599 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_max_level = smc_state_table 3601 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.soc_boot_level = smc_state_table 3603 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.soc_max_level = smc_state_table 3612 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++) smc_state_table 3616 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++) smc_state_table 3619 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++) smc_state_table 3651 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.pp_table.LowGfxclkInterruptThreshold = smc_state_table 3668 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 3967 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_boot_level = smc_state_table 3968 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_max_level = smc_state_table 3970 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_boot_level = smc_state_table 3971 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_max_level = smc_state_table 3989 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_boot_level = smc_state_table 3990 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_max_level = smc_state_table 3992 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_boot_level = smc_state_table 3993 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_max_level = smc_state_table 4012 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_boot_level = smc_state_table 4014 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_max_level = smc_state_table 4016 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_boot_level = smc_state_table 4018 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_max_level = smc_state_table 4085 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0; smc_state_table 4086 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0; smc_state_table 4098 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0; smc_state_table 4099 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0; smc_state_table 4112 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0; smc_state_table 4113 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0; smc_state_table 4357 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c Watermarks_t *table = &(data->smc_state_table.water_marks_table); smc_state_table 4585 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); smc_state_table 4882 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 381 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h struct vega10_smc_state_table smc_state_table; smc_state_table 1291 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PPTable_t *table = &(data->smc_state_table.pp_table); smc_state_table 507 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c PPTable_t *table = &(data->smc_state_table.pp_table); smc_state_table 551 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c (uint8_t *)(&(data->smc_state_table.pp_table)), smc_state_table 562 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c PPTable_t *table = &(data->smc_state_table.pp_table); smc_state_table 576 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c (uint8_t *)(&(data->smc_state_table.pp_table)), smc_state_table 734 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 1866 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c Watermarks_t *table = &(data->smc_state_table.water_marks_table); smc_state_table 2374 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); smc_state_table 2583 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 393 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h struct vega12_smc_state_table smc_state_table; smc_state_table 258 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c PPTable_t *table = &(data->smc_state_table.pp_table); smc_state_table 787 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 1015 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 1216 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table); smc_state_table 1317 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100; smc_state_table 2891 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c Watermarks_t *table = &(data->smc_state_table.water_marks_table); smc_state_table 2914 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c &(data->smc_state_table.overdrive_table); smc_state_table 3257 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c &(data->smc_state_table.overdrive_table); smc_state_table 3547 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); smc_state_table 4120 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 522 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h struct vega20_smc_state_table smc_state_table; smc_state_table 121 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c PPTable_t *pp_table = &(data->smc_state_table.pp_table); smc_state_table 328 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c PPTable_t *table = &(data->smc_state_table.pp_table); smc_state_table 481 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.GraphicsLevel; smc_state_table 491 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; smc_state_table 493 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark = smc_state_table 497 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; smc_state_table 499 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; smc_state_table 718 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); smc_state_table 1013 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.LinkLevelCount = smc_state_table 1309 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel; smc_state_table 1318 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c &(smu_data->smc_state_table.MemoryLevel[i])); smc_state_table 1323 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; smc_state_table 1329 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.MemoryLevel[1].MinVddci = smc_state_table 1330 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.MemoryLevel[0].MinVddci; smc_state_table 1331 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.MemoryLevel[1].MinMvdd = smc_state_table 1332 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.MemoryLevel[0].MinMvdd; smc_state_table 1334 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; smc_state_table 1335 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); smc_state_table 1337 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; smc_state_table 1339 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; smc_state_table 1696 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel)); smc_state_table 1699 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.GraphicsBootLevel = 0; smc_state_table 1706 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel)); smc_state_table 1709 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.MemoryBootLevel = 0; smc_state_table 1863 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.GraphicsBootLevel = level; smc_state_table 1873 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.MemoryBootLevel = level; smc_state_table 1945 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c SMU7_Discrete_DpmTable *table = &(smu_data->smc_state_table); smc_state_table 1950 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table)); smc_state_table 2765 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.GraphicsLevel; smc_state_table 2772 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.MemoryLevel; smc_state_table 2784 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) { smc_state_table 2819 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) { smc_state_table 2869 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.UvdBootLevel = 0; smc_state_table 2871 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.UvdBootLevel = uvd_table->count - 1; smc_state_table 2874 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c UvdBootLevel, smu_data->smc_state_table.UvdBootLevel); smc_state_table 68 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h struct SMU7_Discrete_DpmTable smc_state_table; smc_state_table 492 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); smc_state_table 849 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.LinkLevelCount = smc_state_table 1019 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.GraphicsLevel; smc_state_table 1045 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.GraphicsDpmLevelCount = smc_state_table 1235 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.MemoryLevel; smc_state_table 1260 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.MemoryDpmLevelCount = smc_state_table 1649 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.GraphicsBootLevel = level; smc_state_table 1658 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.MemoryBootLevel = level; smc_state_table 1703 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.ClockStretcherAmount = stretch_amount; smc_state_table 1707 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |= smc_state_table 1718 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; smc_state_table 1746 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq = smc_state_table 1748 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq = smc_state_table 1750 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table. smc_state_table 1751 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1]. smc_state_table 1766 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable. smc_state_table 1768 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable. smc_state_table 1770 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting = smc_state_table 1772 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |= smc_state_table 1783 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.ClockStretcherDataTable. smc_state_table 1786 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.ClockStretcherDataTable. smc_state_table 1792 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) { smc_state_table 1795 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency); smc_state_table 1808 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.ClockStretcherDataTable. smc_state_table 1811 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table. smc_state_table 1930 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table); smc_state_table 2375 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.UvdBootLevel = 0; smc_state_table 2377 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.UvdBootLevel = smc_state_table 2386 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; smc_state_table 2396 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); smc_state_table 2409 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.VceBootLevel = smc_state_table 2412 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.VceBootLevel = 0; smc_state_table 2421 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; smc_state_table 2428 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); smc_state_table 2557 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.GraphicsLevel; smc_state_table 2564 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.MemoryLevel; smc_state_table 2576 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) { smc_state_table 2611 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) { smc_state_table 42 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h struct SMU73_Discrete_DpmTable smc_state_table; smc_state_table 787 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.LinkLevelCount = smc_state_table 970 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; smc_state_table 983 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c &(smu_data->smc_state_table.GraphicsLevel[i])); smc_state_table 989 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; smc_state_table 993 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; smc_state_table 997 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = smc_state_table 1000 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.GraphicsDpmLevelCount = smc_state_table 1027 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; smc_state_table 1031 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; smc_state_table 1034 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; smc_state_table 1356 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel; smc_state_table 1365 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c &(smu_data->smc_state_table.MemoryLevel[i])); smc_state_table 1372 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; smc_state_table 1379 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; smc_state_table 1380 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); smc_state_table 1382 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; smc_state_table 1385 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; smc_state_table 1659 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel)); smc_state_table 1662 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.GraphicsBootLevel = 0; smc_state_table 1669 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel)); smc_state_table 1672 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.MemoryBootLevel = 0; smc_state_table 1831 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.GraphicsBootLevel = level; smc_state_table 1841 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.MemoryBootLevel = level; smc_state_table 1854 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); smc_state_table 1934 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c SMU71_Discrete_DpmTable *table = &(smu_data->smc_state_table); smc_state_table 1938 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table)); smc_state_table 62 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h struct SMU71_Discrete_DpmTable smc_state_table; smc_state_table 429 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); smc_state_table 787 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.LinkLevelCount = smc_state_table 845 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); smc_state_table 992 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.GraphicsLevel; smc_state_table 999 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table)); smc_state_table 1005 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c &(smu_data->smc_state_table.GraphicsLevel[i])); smc_state_table 1015 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; smc_state_table 1017 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; smc_state_table 1018 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.GraphicsDpmLevelCount = smc_state_table 1136 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.MemoryLevel; smc_state_table 1162 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.MemoryDpmLevelCount = smc_state_table 1494 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.GraphicsBootLevel = level; smc_state_table 1503 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.MemoryBootLevel = level; smc_state_table 1557 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |= smc_state_table 1575 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; smc_state_table 1578 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6; smc_state_table 1646 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); smc_state_table 1828 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); smc_state_table 2184 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.UvdBootLevel = 0; smc_state_table 2186 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.UvdBootLevel = smc_state_table 2195 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; smc_state_table 2205 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); smc_state_table 2218 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.VceBootLevel = smc_state_table 2221 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.VceBootLevel = 0; smc_state_table 2230 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; smc_state_table 2237 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); smc_state_table 2470 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.GraphicsLevel; smc_state_table 2477 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.MemoryLevel; smc_state_table 2489 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) { smc_state_table 2524 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) { smc_state_table 57 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h SMU74_Discrete_DpmTable smc_state_table; smc_state_table 530 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.LinkLevelCount = smc_state_table 700 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; smc_state_table 713 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c &(smu_data->smc_state_table.GraphicsLevel[i])); smc_state_table 719 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; smc_state_table 723 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; smc_state_table 727 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = smc_state_table 730 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.GraphicsDpmLevelCount = smc_state_table 741 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = smc_state_table 771 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; smc_state_table 774 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; smc_state_table 777 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; smc_state_table 1102 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.MemoryLevel; smc_state_table 1114 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c &(smu_data->smc_state_table.MemoryLevel[i])); smc_state_table 1120 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; smc_state_table 1127 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; smc_state_table 1128 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); smc_state_table 1130 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; smc_state_table 1133 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; smc_state_table 1192 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.GraphicsLevel[0].MinVoltage; smc_state_table 1242 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.MemoryLevel[0].MinVoltage; smc_state_table 1535 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel)); smc_state_table 1538 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.GraphicsBootLevel = 0; smc_state_table 1547 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel)); smc_state_table 1550 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.MemoryBootLevel = 0; smc_state_table 1616 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.ClockStretcherAmount = stretch_amount; smc_state_table 1621 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |= smc_state_table 1641 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; smc_state_table 1669 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq = smc_state_table 1671 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq = smc_state_table 1673 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table. smc_state_table 1674 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1]. smc_state_table 1689 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable. smc_state_table 1691 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable. smc_state_table 1693 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting = smc_state_table 1695 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |= smc_state_table 1706 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.ClockStretcherDataTable. smc_state_table 1709 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.ClockStretcherDataTable. smc_state_table 1715 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) { smc_state_table 1718 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency); smc_state_table 1729 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.ClockStretcherDataTable. smc_state_table 1732 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table. smc_state_table 1831 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); smc_state_table 2226 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table); smc_state_table 2234 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table)); smc_state_table 2683 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.UvdBootLevel = 0; smc_state_table 2685 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.UvdBootLevel = smc_state_table 2694 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; smc_state_table 2705 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); smc_state_table 2718 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.VceBootLevel = smc_state_table 2728 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; smc_state_table 2736 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); smc_state_table 3153 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.GraphicsLevel; smc_state_table 3160 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.MemoryLevel; smc_state_table 3172 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) { smc_state_table 3207 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) { smc_state_table 66 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h struct SMU72_Discrete_DpmTable smc_state_table; smc_state_table 338 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.UvdBootLevel = 0; smc_state_table 340 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.UvdBootLevel = smc_state_table 349 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; smc_state_table 359 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); smc_state_table 372 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.VceBootLevel = smc_state_table 375 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.VceBootLevel = 0; smc_state_table 384 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; smc_state_table 391 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); smc_state_table 589 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.LinkLevelCount = smc_state_table 720 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table); smc_state_table 876 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.GraphicsLevel; smc_state_table 883 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c vegam_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table)); smc_state_table 889 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c &(smu_data->smc_state_table.GraphicsLevel[i])); smc_state_table 903 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; smc_state_table 905 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.GraphicsDpmLevelCount = smc_state_table 1043 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.MemoryLevel; smc_state_table 1063 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.MemoryDpmLevelCount = smc_state_table 1418 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.GraphicsBootLevel = level; smc_state_table 1427 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.MemoryBootLevel = level; smc_state_table 1447 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table); smc_state_table 1515 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |= smc_state_table 1528 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; smc_state_table 1531 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.LdoRefSel = smc_state_table 1573 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table); smc_state_table 1931 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c struct SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table); smc_state_table 66 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.h SMU75_Discrete_DpmTable smc_state_table; smc_state_table 435 drivers/gpu/drm/radeon/ci_dpm.c SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; smc_state_table 1305 drivers/gpu/drm/radeon/ci_dpm.c SMU7_Discrete_DpmTable *table = &pi->smc_state_table; smc_state_table 2596 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.GraphicsBootLevel = level; smc_state_table 2604 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.MemoryBootLevel = level; smc_state_table 2643 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; smc_state_table 3284 drivers/gpu/drm/radeon/ci_dpm.c SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; smc_state_table 3293 drivers/gpu/drm/radeon/ci_dpm.c &pi->smc_state_table.GraphicsLevel[i]); smc_state_table 3297 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; smc_state_table 3299 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = smc_state_table 3302 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; smc_state_table 3304 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; smc_state_table 3331 drivers/gpu/drm/radeon/ci_dpm.c SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; smc_state_table 3341 drivers/gpu/drm/radeon/ci_dpm.c &pi->smc_state_table.MemoryLevel[i]); smc_state_table 3346 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; smc_state_table 3350 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.MemoryLevel[1].MinVddc = smc_state_table 3351 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.MemoryLevel[0].MinVddc; smc_state_table 3352 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.MemoryLevel[1].MinVddcPhases = smc_state_table 3353 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.MemoryLevel[0].MinVddcPhases; smc_state_table 3356 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); smc_state_table 3358 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; smc_state_table 3362 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = smc_state_table 3560 drivers/gpu/drm/radeon/ci_dpm.c SMU7_Discrete_DpmTable *table = &pi->smc_state_table; smc_state_table 3582 drivers/gpu/drm/radeon/ci_dpm.c ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); smc_state_table 3631 drivers/gpu/drm/radeon/ci_dpm.c (u32 *)&pi->smc_state_table.GraphicsBootLevel); smc_state_table 3635 drivers/gpu/drm/radeon/ci_dpm.c (u32 *)&pi->smc_state_table.MemoryBootLevel); smc_state_table 4085 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.UvdBootLevel = 0; smc_state_table 4087 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.UvdBootLevel = smc_state_table 4092 drivers/gpu/drm/radeon/ci_dpm.c tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); smc_state_table 4127 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); smc_state_table 4130 drivers/gpu/drm/radeon/ci_dpm.c tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); smc_state_table 4156 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.AcpBootLevel = 0; smc_state_table 4160 drivers/gpu/drm/radeon/ci_dpm.c tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel); smc_state_table 5827 drivers/gpu/drm/radeon/ci_dpm.c dpm_table = &pi->smc_state_table; smc_state_table 224 drivers/gpu/drm/radeon/ci_dpm.h SMU7_Discrete_DpmTable smc_state_table;