smc_start_address 226 drivers/gpu/drm/amd/amdgpu/kv_dpm.h u32 smc_start_address, smc_start_address 122 drivers/gpu/drm/amd/amdgpu/kv_smc.c u32 smc_start_address, smc_start_address 128 drivers/gpu/drm/amd/amdgpu/kv_smc.c if ((smc_start_address + byte_count) > limit) smc_start_address 131 drivers/gpu/drm/amd/amdgpu/kv_smc.c addr = smc_start_address; smc_start_address 48 drivers/gpu/drm/amd/amdgpu/si_smc.c u32 smc_start_address, smc_start_address 55 drivers/gpu/drm/amd/amdgpu/si_smc.c if (smc_start_address & 3) smc_start_address 57 drivers/gpu/drm/amd/amdgpu/si_smc.c if ((smc_start_address + byte_count) > limit) smc_start_address 60 drivers/gpu/drm/amd/amdgpu/si_smc.c addr = smc_start_address; smc_start_address 407 drivers/gpu/drm/amd/amdgpu/sislands_smc.h u32 smc_start_address, smc_start_address 108 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, smc_start_address 117 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if ((3 & smc_start_address) smc_start_address 118 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c || ((smc_start_address + byte_count) >= limit)) { smc_start_address 123 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c addr = smc_start_address; smc_start_address 49 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit) smc_start_address 57 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -EINVAL); smc_start_address 58 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -EINVAL); smc_start_address 60 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c addr = smc_start_address; smc_start_address 85 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, smc_start_address 94 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -EINVAL); smc_start_address 95 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -EINVAL); smc_start_address 97 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c addr = smc_start_address; smc_start_address 56 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, smc_start_address 58 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, smc_start_address 326 drivers/gpu/drm/radeon/ci_dpm.h u32 smc_start_address, smc_start_address 48 drivers/gpu/drm/radeon/ci_smc.c u32 smc_start_address, smc_start_address 57 drivers/gpu/drm/radeon/ci_smc.c if (smc_start_address & 3) smc_start_address 59 drivers/gpu/drm/radeon/ci_smc.c if ((smc_start_address + byte_count) > limit) smc_start_address 62 drivers/gpu/drm/radeon/ci_smc.c addr = smc_start_address; smc_start_address 197 drivers/gpu/drm/radeon/kv_dpm.h u32 smc_start_address, smc_start_address 118 drivers/gpu/drm/radeon/kv_smc.c u32 smc_start_address, smc_start_address 124 drivers/gpu/drm/radeon/kv_smc.c if ((smc_start_address + byte_count) > limit) smc_start_address 127 drivers/gpu/drm/radeon/kv_smc.c addr = smc_start_address; smc_start_address 296 drivers/gpu/drm/radeon/rv770_smc.c u16 smc_start_address, const u8 *src, smc_start_address 304 drivers/gpu/drm/radeon/rv770_smc.c if (smc_start_address & 3) smc_start_address 306 drivers/gpu/drm/radeon/rv770_smc.c if ((smc_start_address + byte_count) > limit) smc_start_address 309 drivers/gpu/drm/radeon/rv770_smc.c addr = smc_start_address; smc_start_address 191 drivers/gpu/drm/radeon/rv770_smc.h u16 smc_start_address, const u8 *src, smc_start_address 48 drivers/gpu/drm/radeon/si_smc.c u32 smc_start_address, smc_start_address 55 drivers/gpu/drm/radeon/si_smc.c if (smc_start_address & 3) smc_start_address 57 drivers/gpu/drm/radeon/si_smc.c if ((smc_start_address + byte_count) > limit) smc_start_address 60 drivers/gpu/drm/radeon/si_smc.c addr = smc_start_address; smc_start_address 407 drivers/gpu/drm/radeon/sislands_smc.h u32 smc_start_address,