smc_address       221 drivers/gpu/drm/amd/amdgpu/kv_dpm.h int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
smc_address        78 drivers/gpu/drm/amd/amdgpu/kv_smc.c 				   u32 smc_address, u32 limit)
smc_address        80 drivers/gpu/drm/amd/amdgpu/kv_smc.c 	if (smc_address & 3)
smc_address        82 drivers/gpu/drm/amd/amdgpu/kv_smc.c 	if ((smc_address + 3) > limit)
smc_address        85 drivers/gpu/drm/amd/amdgpu/kv_smc.c 	WREG32(mmSMC_IND_INDEX_0, smc_address);
smc_address        92 drivers/gpu/drm/amd/amdgpu/kv_smc.c int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
smc_address        97 drivers/gpu/drm/amd/amdgpu/kv_smc.c 	ret = kv_set_smc_sram_address(adev, smc_address, limit);
smc_address        34 drivers/gpu/drm/amd/amdgpu/si_smc.c 				   u32 smc_address, u32 limit)
smc_address        36 drivers/gpu/drm/amd/amdgpu/si_smc.c 	if (smc_address & 3)
smc_address        38 drivers/gpu/drm/amd/amdgpu/si_smc.c 	if ((smc_address + 3) > limit)
smc_address        41 drivers/gpu/drm/amd/amdgpu/si_smc.c 	WREG32(SMC_IND_INDEX_0, smc_address);
smc_address       245 drivers/gpu/drm/amd/amdgpu/si_smc.c int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
smc_address       252 drivers/gpu/drm/amd/amdgpu/si_smc.c 	ret = si_set_smc_sram_address(adev, smc_address, limit);
smc_address       260 drivers/gpu/drm/amd/amdgpu/si_smc.c int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
smc_address       267 drivers/gpu/drm/amd/amdgpu/si_smc.c 	ret = si_set_smc_sram_address(adev, smc_address, limit);
smc_address       417 drivers/gpu/drm/amd/amdgpu/sislands_smc.h int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
smc_address       419 drivers/gpu/drm/amd/amdgpu/sislands_smc.h int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
smc_address       110 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 				     uint32_t smc_address, uint32_t limit)
smc_address       115 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (0 != (3 & smc_address)) {
smc_address       120 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (limit <= (smc_address + 3)) {
smc_address       126 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 				SMN_MP1_SRAM_START_ADDR + smc_address);
smc_address       132 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		uint32_t smc_address, uint32_t value, uint32_t limit)
smc_address       139 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	result = smu8_set_smc_sram_address(hwmgr, smc_address, limit);
smc_address       661 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	uint32_t smc_address;
smc_address       671 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smc_address = SMU8_FIRMWARE_HEADER_LOCATION +
smc_address       674 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_write_smc_sram_dword(hwmgr, smc_address, 0, smc_address+4);
smc_address       337 drivers/gpu/drm/radeon/ci_dpm.h 			   u32 smc_address, u32 *value, u32 limit);
smc_address       339 drivers/gpu/drm/radeon/ci_dpm.h 			    u32 smc_address, u32 value, u32 limit);
smc_address        34 drivers/gpu/drm/radeon/ci_smc.c 				   u32 smc_address, u32 limit)
smc_address        36 drivers/gpu/drm/radeon/ci_smc.c 	if (smc_address & 3)
smc_address        38 drivers/gpu/drm/radeon/ci_smc.c 	if ((smc_address + 3) > limit)
smc_address        41 drivers/gpu/drm/radeon/ci_smc.c 	WREG32(SMC_IND_INDEX_0, smc_address);
smc_address       247 drivers/gpu/drm/radeon/ci_smc.c 			   u32 smc_address, u32 *value, u32 limit)
smc_address       253 drivers/gpu/drm/radeon/ci_smc.c 	ret = ci_set_smc_sram_address(rdev, smc_address, limit);
smc_address       262 drivers/gpu/drm/radeon/ci_smc.c 			    u32 smc_address, u32 value, u32 limit)
smc_address       268 drivers/gpu/drm/radeon/ci_smc.c 	ret = ci_set_smc_sram_address(rdev, smc_address, limit);
smc_address       192 drivers/gpu/drm/radeon/kv_dpm.h int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
smc_address        75 drivers/gpu/drm/radeon/kv_smc.c 				   u32 smc_address, u32 limit)
smc_address        77 drivers/gpu/drm/radeon/kv_smc.c 	if (smc_address & 3)
smc_address        79 drivers/gpu/drm/radeon/kv_smc.c 	if ((smc_address + 3) > limit)
smc_address        82 drivers/gpu/drm/radeon/kv_smc.c 	WREG32(SMC_IND_INDEX_0, smc_address);
smc_address        88 drivers/gpu/drm/radeon/kv_smc.c int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
smc_address        93 drivers/gpu/drm/radeon/kv_smc.c 	ret = kv_set_smc_sram_address(rdev, smc_address, limit);
smc_address       278 drivers/gpu/drm/radeon/rv770_smc.c 				      u16 smc_address, u16 limit)
smc_address       282 drivers/gpu/drm/radeon/rv770_smc.c 	if (smc_address & 3)
smc_address       284 drivers/gpu/drm/radeon/rv770_smc.c 	if ((smc_address + 3) > limit)
smc_address       287 drivers/gpu/drm/radeon/rv770_smc.c 	addr = smc_address;
smc_address       604 drivers/gpu/drm/radeon/rv770_smc.c 			      u16 smc_address, u32 *value, u16 limit)
smc_address       610 drivers/gpu/drm/radeon/rv770_smc.c 	ret = rv770_set_smc_sram_address(rdev, smc_address, limit);
smc_address       619 drivers/gpu/drm/radeon/rv770_smc.c 			       u16 smc_address, u32 value, u16 limit)
smc_address       625 drivers/gpu/drm/radeon/rv770_smc.c 	ret = rv770_set_smc_sram_address(rdev, smc_address, limit);
smc_address       201 drivers/gpu/drm/radeon/rv770_smc.h 			      u16 smc_address, u32 *value, u16 limit);
smc_address       203 drivers/gpu/drm/radeon/rv770_smc.h 			       u16 smc_address, u32 value, u16 limit);
smc_address        34 drivers/gpu/drm/radeon/si_smc.c 				   u32 smc_address, u32 limit)
smc_address        36 drivers/gpu/drm/radeon/si_smc.c 	if (smc_address & 3)
smc_address        38 drivers/gpu/drm/radeon/si_smc.c 	if ((smc_address + 3) > limit)
smc_address        41 drivers/gpu/drm/radeon/si_smc.c 	WREG32(SMC_IND_INDEX_0, smc_address);
smc_address       282 drivers/gpu/drm/radeon/si_smc.c int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
smc_address       289 drivers/gpu/drm/radeon/si_smc.c 	ret = si_set_smc_sram_address(rdev, smc_address, limit);
smc_address       297 drivers/gpu/drm/radeon/si_smc.c int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
smc_address       304 drivers/gpu/drm/radeon/si_smc.c 	ret = si_set_smc_sram_address(rdev, smc_address, limit);
smc_address       418 drivers/gpu/drm/radeon/sislands_smc.h int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
smc_address       420 drivers/gpu/drm/radeon/sislands_smc.h int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,