smc_addr          448 arch/mips/txx9/rbtx4939/setup.c 	unsigned long smc_addr = RBTX4939_ETHER_ADDR - IO_BASE;
smc_addr          451 arch/mips/txx9/rbtx4939/setup.c 			.start	= smc_addr,
smc_addr          452 arch/mips/txx9/rbtx4939/setup.c 			.end	= smc_addr + 0x10 - 1,
smc_addr           95 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 					uint32_t smc_addr, uint32_t limit)
smc_addr           97 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if ((0 != (3 & smc_addr))
smc_addr           98 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		|| ((smc_addr + 3) >= limit)) {
smc_addr          103 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr);
smc_addr          194 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
smc_addr          199 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_set_smc_sram_address(hwmgr, smc_addr, limit);
smc_addr           38 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit)
smc_addr           40 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
smc_addr           41 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
smc_addr           43 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr);
smc_addr          280 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
smc_addr          284 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
smc_addr          291 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
smc_addr          295 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
smc_addr           71 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
smc_addr           73 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,