sm_cfg             83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct mpcc_sm_cfg *sm_cfg,
sm_cfg             89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			MPCC_SM_EN,			sm_cfg->enable,
sm_cfg             90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			MPCC_SM_MODE,			sm_cfg->sm_mode,
sm_cfg             91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			MPCC_SM_FRAME_ALT,		sm_cfg->frame_alt,
sm_cfg             92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			MPCC_SM_FIELD_ALT,		sm_cfg->field_alt,
sm_cfg             93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			MPCC_SM_FORCE_NEXT_FRAME_POL,	sm_cfg->force_next_frame_porlarity,
sm_cfg             94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			MPCC_SM_FORCE_NEXT_TOP_POL,	sm_cfg->force_next_field_polarity);
sm_cfg            180 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	struct mpcc_sm_cfg *sm_cfg,
sm_cfg            243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	if (sm_cfg != NULL) {
sm_cfg            244 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		new_mpcc->sm_cfg = *sm_cfg;
sm_cfg            245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id);
sm_cfg            335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	mpcc->sm_cfg.enable = false;
sm_cfg            139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	struct mpcc_sm_cfg *sm_cfg,
sm_cfg            167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	struct mpcc_sm_cfg *sm_cfg,
sm_cfg            481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	mpcc->sm_cfg.enable = false;
sm_cfg            113 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h 	struct mpcc_sm_cfg sm_cfg;	/* stereo mix setting for this MPCC */
sm_cfg            173 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h 			struct mpcc_sm_cfg *sm_cfg,