CM0_CM_IGAM_LUT_RW_CONTROL  422 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \
CM0_CM_IGAM_LUT_RW_CONTROL  423 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
CM0_CM_IGAM_LUT_RW_CONTROL  424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \
CM0_CM_IGAM_LUT_RW_CONTROL  425 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \
CM0_CM_IGAM_LUT_RW_CONTROL  426 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \