slices 556 arch/arm64/kvm/guest.c const unsigned int slices = vcpu_sve_slices(vcpu); slices 564 arch/arm64/kvm/guest.c return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */) slices 571 arch/arm64/kvm/guest.c const unsigned int slices = vcpu_sve_slices(vcpu); slices 591 arch/arm64/kvm/guest.c for (i = 0; i < slices; i++) { slices 52 block/partitions/sysv68.c int i, slices; slices 69 block/partitions/sysv68.c slices = be16_to_cpu(b->dk_ios.ios_slccnt); slices 77 block/partitions/sysv68.c slices -= 1; /* last slice is the whole disk */ slices 78 block/partitions/sysv68.c snprintf(tmp, sizeof(tmp), "sysV68: %s(s%u)", state->name, slices); slices 81 block/partitions/sysv68.c for (i = 0; i < slices; i++, slice++) { slices 1805 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; slices 1817 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c slices, slices 1831 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c slices / 2.0, slices 4227 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.slices = 0; slices 4230 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.slices = 0; slices 4232 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.slices = dml_ceil( slices 4236 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.slices = 8.0; slices 4238 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.slices = 4.0; slices 4240 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.slices = 2.0; slices 4242 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.slices = 1.0; slices 4258 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.slices, slices 4260 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.slices, slices 4269 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), slices 4270 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.slices / 2, slices 1840 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; slices 1852 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c slices, slices 1866 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c slices / 2.0, slices 4259 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.slices = 0; slices 4262 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.slices = 0; slices 4264 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.slices = dml_ceil( slices 4268 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.slices = 8.0; slices 4270 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.slices = 4.0; slices 4272 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.slices = 2.0; slices 4274 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.slices = 1.0; slices 4290 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.slices, slices 4292 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.slices, slices 4301 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), slices 4302 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.slices / 2, slices 1792 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; slices 1804 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c slices, slices 1818 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c slices / 2.0, slices 4306 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.slices = 0; slices 4309 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.slices = 0; slices 4311 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.slices = dml_ceil( slices 4315 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.slices = 8.0; slices 4317 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.slices = 4.0; slices 4319 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.slices = 2.0; slices 4321 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.slices = 1.0; slices 4337 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.slices, slices 4339 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.slices, slices 4348 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), slices 4349 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.slices / 2, slices 465 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h unsigned int slices; slices 807 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c __check_rpcs(const char *name, u32 rpcs, int slices, unsigned int expected, slices 810 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c if (slices == expected) slices 813 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c if (slices < 0) { slices 815 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c name, prefix, slices, suffix); slices 816 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c return slices; slices 820 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c name, prefix, slices, expected, suffix); slices 823 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c rpcs, slices, slices 839 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c unsigned int slices = hweight32(ce->engine->sseu.slice_mask); slices 856 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c ret = __check_rpcs(name, rpcs, ret, slices, "Kernel context", "!"); slices 34 drivers/gpu/drm/i915/gt/intel_sseu.c u8 slices, subslices; slices 69 drivers/gpu/drm/i915/gt/intel_sseu.c slices = hweight8(ctx_sseu.slice_mask); slices 98 drivers/gpu/drm/i915/gt/intel_sseu.c slices == 1 && slices 103 drivers/gpu/drm/i915/gt/intel_sseu.c slices *= 2; slices 113 drivers/gpu/drm/i915/gt/intel_sseu.c u32 mask, val = slices; slices 695 drivers/misc/cxl/cxl.h u8 slices; slices 57 drivers/misc/cxl/file.c if (slice > adapter->slices) slices 348 drivers/misc/cxl/flash.c for (afu = 0; afu < adapter->slices; afu++) slices 267 drivers/misc/cxl/guest.c for (i = 0; i < adapter->slices; i++) { slices 276 drivers/misc/cxl/guest.c for (i = 0; i < adapter->slices; i++) { slices 937 drivers/misc/cxl/guest.c adapter->slices++; slices 1109 drivers/misc/cxl/guest.c adapter->slices = 0; slices 88 drivers/misc/cxl/main.c for (slice = 0; slice < adapter->slices; slice++) { slices 441 drivers/misc/cxl/of.c for (afu = 0; afu < adapter->slices; afu++) slices 486 drivers/misc/cxl/of.c adapter->slices = 0; slices 1316 drivers/misc/cxl/pci.c CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices); slices 1330 drivers/misc/cxl/pci.c adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices; slices 1388 drivers/misc/cxl/pci.c if (!adapter->slices) { slices 1566 drivers/misc/cxl/pci.c for (slice = 0; slice < adapter->slices; slice++) { slices 1763 drivers/misc/cxl/pci.c for (slice = 0; slice < adapter->slices; slice++) { slices 1787 drivers/misc/cxl/pci.c for (i = 0; i < adapter->slices; i++) { slices 1844 drivers/misc/cxl/pci.c for (i = 0; i < adapter->slices; i++) { slices 1938 drivers/misc/cxl/pci.c for (i = 0; i < adapter->slices; i++) { slices 1990 drivers/misc/cxl/pci.c for (i = 0; i < adapter->slices; i++) { slices 2070 drivers/misc/cxl/pci.c for (i = 0; i < adapter->slices; i++) { slices 27 drivers/net/dsa/bcm_sf2_cfp.c u8 slices[UDFS_PER_SLICE]; slices 42 drivers/net/dsa/bcm_sf2_cfp.c .slices = { slices 67 drivers/net/dsa/bcm_sf2_cfp.c .slices = { slices 91 drivers/net/dsa/bcm_sf2_cfp.c .slices = { slices 147 drivers/net/dsa/bcm_sf2_cfp.c if (memcmp(slice_layout->slices, zero_slice, slices 163 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, layout->udfs[slice_num].slices[i], slices 390 drivers/net/dsa/bcm_sf2_cfp.c num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices); slices 631 drivers/net/dsa/bcm_sf2_cfp.c num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices); slices 744 drivers/net/dsa/bcm_sf2_cfp.c num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices); slices 202 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c static const struct reg_default slices[] = { slices 218 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c for (i = 0; i < ARRAY_SIZE(slices); i++) { slices 220 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c regmap_update_bits(priv->phy_regmap, slices[i].reg, slices 221 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c slices[i].def, slices[i].def); slices 226 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c regmap_update_bits(priv->phy_regmap, slices[i].reg, slices 227 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c slices[i].def, 0x0); slices 26 drivers/staging/media/hantro/hantro_g1_h264_dec.c const struct v4l2_ctrl_h264_slice_params *slices = ctrls->slices; slices 45 drivers/staging/media/hantro/hantro_g1_h264_dec.c slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC)) slices 47 drivers/staging/media/hantro/hantro_g1_h264_dec.c if (slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) slices 49 drivers/staging/media/hantro/hantro_g1_h264_dec.c if (!(slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)) slices 78 drivers/staging/media/hantro/hantro_g1_h264_dec.c G1_REG_DEC_CTRL4_FRAMENUM(slices[0].frame_num) | slices 91 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = G1_REG_DEC_CTRL5_REFPIC_MK_LEN(slices[0].dec_ref_pic_marking_bit_size) | slices 92 drivers/staging/media/hantro/hantro_g1_h264_dec.c G1_REG_DEC_CTRL5_IDR_PIC_ID(slices[0].idr_pic_id); slices 106 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = G1_REG_DEC_CTRL6_PPS_ID(slices[0].pic_parameter_set_id) | slices 109 drivers/staging/media/hantro/hantro_g1_h264_dec.c G1_REG_DEC_CTRL6_POC_LENGTH(slices[0].pic_order_cnt_bit_size); slices 255 drivers/staging/media/hantro/hantro_g1_h264_dec.c if (ctrls->slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) slices 281 drivers/staging/media/hantro/hantro_h264.c slice_params = &ctx->h264_dec.ctrls.slices[0]; slices 579 drivers/staging/media/hantro/hantro_h264.c ctrls->slices = slices 581 drivers/staging/media/hantro/hantro_h264.c if (WARN_ON(!ctrls->slices)) slices 60 drivers/staging/media/hantro/hantro_hw.h const struct v4l2_ctrl_h264_slice_params *slices; slices 587 drivers/usb/dwc2/hcd_queue.c int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE); slices 607 drivers/usb/dwc2/hcd_queue.c DWC2_LS_SCHEDULE_FRAMES, slices, slices 626 drivers/usb/dwc2/hcd_queue.c int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE); slices 634 drivers/usb/dwc2/hcd_queue.c DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval,