slice_width       363 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	DC_LOG_DSC("\tslice_width %d", config->slice_width);
slice_width       427 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 									dsc_optc_cfg.slice_width);
slice_width       438 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 							dsc_optc_cfg.slice_width);
slice_width       270 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	DC_LOG_DSC("\tslice_width %d", pps->slice_width);
slice_width       354 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
slice_width       382 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;
slice_width       476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	reg_vals->pps.slice_width                 = 0;
slice_width       579 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		SLICE_WIDTH, reg_vals->pps.slice_width,
slice_width       522 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	int slice_width;
slice_width       675 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	slice_width = pic_width / num_slices_h;
slice_width       677 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	is_dsc_possible = slice_width <= dsc_common_caps.max_slice_width;
slice_width       176 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_comp bpc, float bpp, int slice_width, int slice_height, int minor_version)
slice_width       212 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c 		slice_width /= 2;
slice_width       214 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c 	padding_pixels = ((slice_width % 3) != 0) ? (3 - (slice_width % 3)) * (rc->initial_xmit_delay / slice_width) : 0;
slice_width        81 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_comp bpc, float bpp, int slice_width, int slice_height, int minor_version);
slice_width        38 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	to->slice_width              = from->slice_width;
slice_width       111 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	int              slice_width  = pps->slice_width;
slice_width       117 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	double d_bytes_per_pixel = dsc_ceil(bpp * slice_width / 8.0) / slice_width;
slice_width       131 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	calc_rc_params(&rc, mode, bpc, bpp, slice_width, slice_height, pps->dsc_version_minor);
slice_width        45 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h 	uint32_t slice_width; /* Slice width in pixels */
slice_width       122 drivers/gpu/drm/drm_dsc.c 	pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
slice_width       270 drivers/gpu/drm/drm_dsc.c 		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
slice_width       274 drivers/gpu/drm/drm_dsc.c 		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
slice_width       279 drivers/gpu/drm/drm_dsc.c 		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
slice_width       283 drivers/gpu/drm/drm_dsc.c 		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
slice_width       334 drivers/gpu/drm/i915/display/intel_vdsc.c 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
slice_width       568 drivers/gpu/drm/i915/display/intel_vdsc.c 		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
slice_width       733 drivers/gpu/drm/i915/display/intel_vdsc.c 				   vdsc_cfg->slice_width) |
slice_width      11300 drivers/gpu/drm/i915/i915_reg.h #define  DSC_SLICE_WIDTH(slice_width)   ((slice_width) << 16)
slice_width        98 include/drm/drm_dsc.h 	u16 slice_width;
slice_width       357 include/drm/drm_dsc.h 	__be16 slice_width;