slice_height      269 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	DC_LOG_DSC("\tslice_height %d", pps->slice_height);
slice_height      355 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
slice_height      357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
slice_height      358 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
slice_height      477 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	reg_vals->pps.slice_height                = 0;
slice_height      580 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		SLICE_HEIGHT, reg_vals->pps.slice_height);
slice_height      528 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	int slice_height;
slice_height      683 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	slice_height = min(dsc_policy.min_sice_height, pic_height);
slice_height      685 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	while (slice_height < pic_height && (pic_height % slice_height != 0 ||
slice_height      686 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		(timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && slice_height % 2 != 0)))
slice_height      687 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		slice_height++;
slice_height      690 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		is_dsc_possible = (slice_height % 2 == 0);
slice_height      695 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_cfg->num_slices_v = pic_height/slice_height;
slice_height      176 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_comp bpc, float bpp, int slice_width, int slice_height, int minor_version)
slice_height      192 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c 		rc->first_line_bpg_offset   = median3(0, (12 + (int) (0.09 *  min(34, slice_height - 8))), (int)((3 * bpc * 3) - (3 * bpp_group)));
slice_height      197 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c 		rc->first_line_bpg_offset   = median3(0, (12 + (int) (0.09 *  min(34, slice_height - 8))), (int)((3 * bpc * 4) - (3 * bpp_group)));
slice_height      203 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c 		rc->first_line_bpg_offset   = median3(0, (12 + (int) (0.09 *  min(34, slice_height - 8))), (int)(((3 * bpc + (cm == CM_444 ? 0 : 2)) * 3) - (3 * bpp_group)));
slice_height       81 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_comp bpc, float bpp, int slice_width, int slice_height, int minor_version);
slice_height       39 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	to->slice_height             = from->slice_height;
slice_height      112 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	int              slice_height = pps->slice_height;
slice_height      131 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	calc_rc_params(&rc, mode, bpc, bpp, slice_width, slice_height, pps->dsc_version_minor);
slice_height      119 drivers/gpu/drm/drm_dsc.c 	pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
slice_height      301 drivers/gpu/drm/drm_dsc.c 	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
slice_height      328 drivers/gpu/drm/drm_dsc.c 	if (vdsc_cfg->slice_height > 1)
slice_height      335 drivers/gpu/drm/drm_dsc.c 							(vdsc_cfg->slice_height - 1));
slice_height      346 drivers/gpu/drm/drm_dsc.c 	groups_total = groups_per_line * vdsc_cfg->slice_height;
slice_height      342 drivers/gpu/drm/i915/display/intel_vdsc.c 		vdsc_cfg->slice_height = 8;
slice_height      344 drivers/gpu/drm/i915/display/intel_vdsc.c 		vdsc_cfg->slice_height = 4;
slice_height      346 drivers/gpu/drm/i915/display/intel_vdsc.c 		vdsc_cfg->slice_height = 2;
slice_height      567 drivers/gpu/drm/i915/display/intel_vdsc.c 	pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
slice_height      735 drivers/gpu/drm/i915/display/intel_vdsc.c 					vdsc_cfg->slice_height);
slice_height     11301 drivers/gpu/drm/i915/i915_reg.h #define  DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
slice_height      102 include/drm/drm_dsc.h 	u16 slice_height;
slice_height      352 include/drm/drm_dsc.h 	__be16 slice_height;